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    DATA NEGOTIATION USING SERIAL VOLTAGE IDENTIFICATION COMMUNICATION
    9.
    发明申请
    DATA NEGOTIATION USING SERIAL VOLTAGE IDENTIFICATION COMMUNICATION 有权
    使用串行电压鉴定通信的数据协商

    公开(公告)号：US20110154075A1

    公开(公告)日：2011-06-23

    申请号：US12912924

    申请日：2010-10-27

    申请人： Waseem S. Kraipak ,  Jayesh Iyer ,  Edward R. Stanford

    发明人： Waseem S. Kraipak ,  Jayesh Iyer ,  Edward R. Stanford

    IPC分类号： G06F1/32 ,  G06F1/26

    CPC分类号： G06F13/4291

    摘要： According to some embodiments, a method and system are provided to initiate communication at an integrated circuit that is electrically coupled to a plurality of voltage regulators, determine a slowest one of the plurality of voltage regulators that is electrically coupled to the processor, transmit address information to the plurality of voltage regulators that are electrically coupled to the processor at a first speed associated with the slowest one of the plurality of voltage regulators, determine a second speed associated with a voltage regulator to which the address information is associated, and transmit a second portion of the packet at the second speed associated with the voltage regulator to which the address information is associated.

    摘要翻译： 根据一些实施例，提供了一种方法和系统以在集成电路中启动通信，该集成电路电耦合到多个稳压器，确定电耦合到处理器的多个电压调节器中最慢的电压调节器，发送地址信息 以与所述多个电压调节器中最慢速度相关联的第一速度电耦合到所述处理器的所述多个电压调节器确定与所述地址信息相关联的电压调节器相关联的第二速度，并且发送第二 以与地址信息相关联的电压调节器相关联的第二速度的分组的部分。

    System and method for memory phase shedding
    10.
    发明授权
    System and method for memory phase shedding 有权
    内存相位脱落的系统和方法

    公开(公告)号：US07804733B2

    公开(公告)日：2010-09-28

    申请号：US11968142

    申请日：2007-12-31

    申请人： James W. Alexander ,  Edward R. Stanford ,  Devadatta V. Bodas ,  Howard David ,  Son H. Lam

    发明人： James W. Alexander ,  Edward R. Stanford ,  Devadatta V. Bodas ,  Howard David ,  Son H. Lam

    IPC分类号： G11C7/00

    CPC分类号： G06F1/26 ,  G06F1/3225

    摘要： Embodiments of the invention supply power to DRAM or other memory devices with a multi-phase voltage regulator. A power controller coupled to the multi-phase voltage regulator causes one or more phases of the multi-phase voltage regulator to be activated or deactivated (shed) according to predetermined criteria. Embodiments of the invention thus improve power management by providing one or more reduced power states for the memory devices. Other embodiments are described.

    摘要翻译： 本发明的实施例用多相电压调节器向DRAM或其他存储器件供电。 耦合到多相电压调节器的功率控制器根据预定标准使多相电压调节器的一个或多个相位被激活或去激活（脱落）。 因此，本发明的实施例通过为存储器件提供一个或多个降低的功率状态来改善功率管理。 描述其他实施例。