公开(公告)号：US07711911B2

公开(公告)日：2010-05-04

申请号：US11602976

申请日：2006-11-22

申请人： Hajime Takahashi

发明人： Hajime Takahashi

IPC分类号： G06F12/16 ,  G06F7/02

CPC分类号： G06F11/2097 ,  G06F11/2038 ,  H04L67/1002 ,  H04L67/1034 ,  H04L69/40

摘要： A single information processing device capable of configuring an information system that maintains matching between information retained by a self device and information retained by a partner device in a way that links up a plurality of information processing devices with each other, has a storage unit including a memory cell retaining a predetermined quantity of information and a comparing unit that compares the information retained by the memory cell at the present with information written afresh to the memory cell, an extraction unit extracting the information written afresh to the memory cell about which the comparing unit judges that the information retained at the present is different from the information written afresh, and a transmitting unit transmitting the extracted information to the partner device linking up with the self device.

摘要翻译： 能够配置信息系统的单个信息处理装置具有保持由自身装置保存的信息与由对方装置保持的信息之间的匹配的信息系统，该信息处理装置具有将多个信息处理装置彼此连接的方式，具有包括 存储单元保持预定量的信息;以及比较单元，将当前存储单元保留的信息与新写入的信息进行比较，提取单元将重新写入的信息提取到存储单元 判断当前保留的信息与重新写入的信息不同，发送单元将提取的信息发送到与自身设备连接的对方设备。

公开(公告)号：US07368891B2

公开(公告)日：2008-05-06

申请号：US11341856

申请日：2006-01-30

申请人： Hajime Takahashi ,  Kazuhiko Hiramatsu

发明人： Hajime Takahashi ,  Kazuhiko Hiramatsu

IPC分类号： H02J7/00

CPC分类号： H02M7/125

摘要： Charging time of a capacitor is shortened while avoiding erroneous firing due to distortion of a power supply voltage and sustaining an inrush current at a constant level. In the charge control method of a capacitor in a thyristor converter comprising a thyristor for rectifying an AC voltage, a CPU delivering an on/off control signal to a thyristor driver for driving the thyristor, a voltage detection sensor for measuring the AC voltage and the capacitor charging voltage, and the capacitor connected with a DC circuit, the AC voltage and the capacitor charging voltage are measured by means of the voltage detection sensor, differential voltage between the firing phase voltage of the thyristor and the capacitor charging voltage is determined, and the thyristor is fired only when the firing phase voltage of the thyristor becomes lower than a specified voltage determined from the differential voltage.

摘要翻译： 缩短电容器的充电时间，同时避免由于电源电压的失真而引起的错误点火，并且将浪涌电流维持在恒定水平。 在包括用于整流交流电压的晶闸管的晶闸管转换器中的电容器的充电控制方法中，将用于驱动晶闸管的晶闸管驱动器提供导通/截止控制信号的CPU，用于测量交流电压的电压检测传感器和 电容器充电电压和与直流电路连接的电容器，通过电压检测传感器测量交流电压和电容器充电电压，确定晶闸管的点火相电压与电容器充电电压之间的差分电压，以及 只有当晶闸管的点火相电压变得低于从差分电压确定的规定电压时，晶闸管才被烧断。

公开(公告)号：US5761728A

公开(公告)日：1998-06-02

申请号：US777184

申请日：1996-12-27

申请人： Hiroshi Saito ,  Takatsugu Sasaki ,  Hirohide Sugahara ,  Akira Kabemoto ,  Hajime Takahashi ,  Jun Funaki

发明人： Hiroshi Saito ,  Takatsugu Sasaki ,  Hirohide Sugahara ,  Akira Kabemoto ,  Hajime Takahashi ,  Jun Funaki

IPC分类号： G06F12/00 ,  G06F13/16 ,  G06F15/16 ,  G06F9/38

CPC分类号： G06F13/1673

摘要： An asynchronous access system for a computer system includes processing modules performing processes, at least one shared system memory module, and a system bus connecting the processing modules and the shared system memory module. Each of the processing modules includes a processor, a plurality of buffers coupled to the processor and to the system bus, and a controlling unit for writing data from the plurality of processors into the shared system memory module. Data is written into the shared system memory module by a processor generating write instructions to write data via the plurality of buffers and the system bus. The controlling unit controls the writing such that one writing instruction writes data into a plurality of buffers, then transfers the data to the shared system memory module via the system bus, with another writing instruction writing additional data into another plurality of buffers and transferring the additional data to the shared system memory module.

摘要翻译： 用于计算机系统的异步访问系统包括执行处理的处理模块，至少一个共享系统存储器模块以及连接处理模块和共享系统存储器模块的系统总线。 每个处理模块包括处理器，耦合到处理器和系统总线的多个缓冲器，以及用于将数据从多个处理器写入共享系统存储器模块的控制单元。 通过处理器将数据写入共享系统存储器模块，该处理器产生写入指令以经由多个缓冲器和系统总线写入数据。 控制单元控制写入，使得一个写入指令将数据写入多个缓冲器，然后经由系统总线将数据传送到共享系统存储器模块，另一个写入指令将另外的数据写入另一个多个缓冲器并传送附加的数据 数据到共享系统内存模块。

公开(公告)号：US5592624A

公开(公告)日：1997-01-07

申请号：US859318

申请日：1992-05-28

申请人： Hajime Takahashi ,  Hirohide Sugahara ,  Akira Kabemoto

发明人： Hajime Takahashi ,  Hirohide Sugahara ,  Akira Kabemoto

IPC分类号： G06F15/17 ,  G06F13/00 ,  G06F13/14

CPC分类号： G06F15/17

摘要： A message control system for a data communication system in the form of a loosely coupled multiprocessing system, in which a plurality of processing modules having a memory unit are coupled to each other via a system bus. In this message control system, a memory unit, within each processing module, includes a data processing part which is in software running on a central processing unit within its own processing module, a descriptor which manages address and data length information of a storage region for a message in the form of a chain, and a buffer which decomposes and stores a transmitting message. A connection unit within each processing module includes logical transmitting ports and a logical receiving port.

摘要翻译： PCT No.PCT / JP91 / 01306 Sec。 371日期：1992年5月28日 102（e）日期1992年5月28日PCT 1991年9月27日PCT公布。 出版物WO92 / 06430 日期1992年04月16日用于松散耦合的多处理系统形式的数据通信系统的消息控制系统，其中具有存储器单元的多个处理模块经由系统总线相互耦合。 在该消息控制系统中，每个处理模块内的存储器单元包括在其自身的处理模块内的中央处理单元上运行的软件的数据处理部，管理存储区域的地址和数据长度信息的描述符， 以链的形式的消息，以及分解和存储发送消息的缓冲器。 每个处理模块内的连接单元包括逻辑发送端口和逻辑接收端口。

公开(公告)号：US5410650A

公开(公告)日：1995-04-25

申请号：US859319

申请日：1992-05-28

申请人： Takatsugu Sasaki ,  Akira Kabemoto ,  Hajime Takahashi ,  Horihide Sugahara

发明人： Takatsugu Sasaki ,  Akira Kabemoto ,  Hajime Takahashi ,  Horihide Sugahara

IPC分类号： G06F13/12 ,  G06F15/17 ,  G06F13/00

CPC分类号： G06F15/17 ,  G06F13/128

摘要： A message control system for a data communication system which takes the form of a loosely coupled multiprocessing system in which a plurality of processing modules respectively having a memory unit are coupled to each other via a system bus. In the message control system, each processing module (10, 40) includes a central processing unit (11, 41), a memory unit (12, 42) and a connection unit (13, 43). The connection unit (13, 43) includes at least a logical transmitting port (21, 51) for transmitting a message, a logical receiving port (22, 53) for receiving a message, a transmission system connecting unit (23), a reception system connecting unit (24), a transmitting side fault generation monitoring unit (25) and a receiving side fault generation monitoring unit (26).

摘要翻译： PCT No.PCT / JP91 / 01307 Sec。 371日期：1992年5月28日 102（e）日期1992年5月28日PCT 1991年9月27日PCT公布。 公开号WO92 / 06431 日期：1992年4月16日。一种用于数据通信系统的消息控制系统，其采取松散耦合的多处理系统的形式，其中分别具有存储器单元的多个处理模块经由系统总线彼此耦合。 在消息控制系统中，每个处理模块（10,40）包括中央处理单元（11,41），存储单元（12,42）和连接单元（13,43）。 连接单元（13,43）至少包括用于发送消息的逻辑发送端口（21,51），用于接收消息的逻辑接收端口（22,53），发送系统连接单元（23），接收 系统连接单元（24），发送侧故障生成监视单元（25）和接收侧故障生成监视单元（26）。

公开(公告)号：US07830206B2

公开(公告)日：2010-11-09

申请号：US11863710

申请日：2007-09-28

申请人： Hajime Takahashi ,  Hiroshi Ikeda

发明人： Hajime Takahashi ,  Hiroshi Ikeda

IPC分类号： H03F1/26

CPC分类号： H03F1/305 ,  H03F3/187 ,  H03F3/45475 ,  H03F2200/03 ,  H03F2203/45138

摘要： An extraction circuit is connected to an input path of an output amplifier. When the power is turned on, the extraction circuit extracts current on the basis of a difference between the normal rise of the supply voltage and a delayed supply voltage. Therefore, a steep rise in the input of the output amplifier when the power is turned on can be removed.

摘要翻译： 提取电路连接到输出放大器的输入路径。 当电源接通时，提取电路基于电源电压的正常上升与延迟的电源电压之间的差异来提取电流。 因此，可以消除电源接通时输出放大器的输入的急剧上升。

公开(公告)号：US20100210360A1

公开(公告)日：2010-08-19

申请号：US12772549

申请日：2010-05-03

申请人： Hajime TAKAHASHI ,  Gentaro TAKAKI

发明人： Hajime TAKAHASHI ,  Gentaro TAKAKI

IPC分类号： A63F13/00 ,  A63F9/24

CPC分类号： A63F13/58 ,  A63F13/10 ,  A63F13/2145 ,  A63F13/26 ,  A63F13/822 ,  A63F13/92 ,  A63F13/95 ,  A63F2300/1075 ,  A63F2300/301 ,  A63F2300/65 ,  A63F2300/807

摘要： When a player character performs an act tendency (boom) triggering act, the act number counters are updated for each non-player character associated with the boom triggering act. The value of each act number counter is periodically added to an act tendency value for each non-player character. After an act tendency value reaches an upper limit, the corresponding non-player character performs an act in response to the act tendency triggering act performed by the player character. The act of each non-player character is changed in accordance with the acts performed by the player character in the game world, which provides the player with a fresh feeling that the act performed by the player character set a trend in the game world.

摘要翻译： 当玩家角色执行动作趋势（繁荣）触发动作时，针对与吊杆触发动作相关联的每个非玩家角色更新动作号码计数器。 每个动作号码计数器的值被定期地添加到每个非玩家角色的动作趋势值。 在动作趋势值达到上限之后，对应的非玩家角色响应于玩家角色执行的动作趋势触发动作执行动作。 每个非玩家角色的行为根据游戏世界中的玩家角色所执行的动作而改变，这为玩家提供了玩家角色所执行的动作在游戏世界中设定趋势的新感觉。

公开(公告)号：US20100045373A1

公开(公告)日：2010-02-25

申请号：US11863710

申请日：2007-09-28

申请人： Hajime Takahashi ,  Hiroshi Ikeda

发明人： Hajime Takahashi ,  Hiroshi Ikeda

IPC分类号： H03F3/68

CPC分类号： H03F1/305 ,  H03F3/187 ,  H03F3/45475 ,  H03F2200/03 ,  H03F2203/45138

摘要： An extraction circuit is connected to an input path of an output amplifier. When the power is turned on, the extraction circuit extracts current on the basis of a difference between the normal rise of the supply voltage and a delayed supply voltage. Therefore, a steep rise in the input of the output amplifier when the power is turned on can be removed.

摘要翻译： 提取电路连接到输出放大器的输入路径。 当电源接通时，提取电路基于电源电压的正常上升与延迟的电源电压之间的差异来提取电流。 因此，可以消除电源接通时输出放大器的输入的急剧上升。

公开(公告)号：US20090161393A1

公开(公告)日：2009-06-25

申请号：US12295926

申请日：2007-03-06

申请人： Hajime Takahashi ,  Mitsujiro Sawamura

发明人： Hajime Takahashi ,  Mitsujiro Sawamura

IPC分类号： H02M1/12

CPC分类号： H02M7/5395 ,  H03K7/08

摘要： There is provided a PWM inverter capable of preventing a phase error from occurring in generating a PWM signal even in the case where a carrier wave frequency is not sufficiently higher than a signal wave frequency. A PWM signal generating section (2) includes a phase adjusting section (11) configured to advance a phase of the signal wave by adding, to a signal wave, a delay component of the PWM signal with respect to the signal wave, the phase delay component being involved by digital control. Furthermore, in a case where the carrier wave frequency is changed, the phase delay component with respect to the signal wave is updated in synchronism with the timing of change of the carrier wave frequency.

摘要翻译： 即使在载波频率不足够高于信号波频率的情况下，也能够防止在产生PWM信号时发生相位误差的PWM逆变器。 PWM信号产生部分（2）包括相位调整部分（11），被配置为通过将相对于信号波的PWM信号的延迟分量加到信号波上来推进信号波的相位，相位延迟 组件涉及数字控制。 此外，在载波频率变化的情况下，相对于信号波的相位延迟分量与载波频率的变化的定时同步地更新。

公开(公告)号：US20090039963A1

公开(公告)日：2009-02-12

申请号：US11863881

申请日：2007-09-28

申请人： Hajime Takahashi ,  Hiroshi Ikeda

发明人： Hajime Takahashi ,  Hiroshi Ikeda

IPC分类号： H03F1/52

CPC分类号： H03F1/52 ,  H03F3/3081 ,  H03F2200/03 ,  H03F2200/444 ,  H03F2200/462 ,  H03F2200/471

摘要： A power amplifier drives a load connected to a first output terminal and a second output terminal. When generation of over-current is detected by the current detection section, the output amplifier control section is controlled to stop the operation of the output amplifier section, and when a voltage greater than or equal to said set value is detected by said voltage detection section, the stopped operation of said output amplifier section is maintained even though generation of the over-current is not detected at the current detection section. When the terminal voltage detection section detects a terminal voltage greater than or equal to a predetermined voltage, over-current at the current detection section is suppressed.

摘要翻译： 功率放大器驱动连接到第一输出端子和第二输出端子的负载。 当由电流检测部分检测到过电流的产生时，控制输出放大器控制部分以停止输出放大器部分的操作，并且当所述电压检测部分检测到大于或等于所述设定值的电压时 即使在当前检测部分没有检测到过电流的产生，也保持所述输出放大器部分的停止操作。 当端子电压检测部分检测到大于或等于预定电压的端子电压时，电流检测部分处的过电流被抑制。