Method for monitoring a CMP polishing method and arrangement for a CMP polishing method
    1.
    发明申请
    Method for monitoring a CMP polishing method and arrangement for a CMP polishing method 审中-公开
    CMP抛光方法的监测方法和CMP抛光方法的布置方法

    公开(公告)号:US20060141907A1

    公开(公告)日:2006-06-29

    申请号:US11291067

    申请日:2005-12-01

    IPC分类号: B24B49/00 B24B7/30

    摘要: The invention relates to a method for monitoring a CMP polishing method, a substrate being fixed in a mount, a polishing pad being fixed on a plate, a surface of the polishing pad being operatively connected to a surface of the substrate, the polishing pad and the substrate being moved relative to one another, so that material is removed from the surface of the substrate. A measuring device is provided, which is operatively connected to the surface of the polishing pad, the measuring device detecting the surface constitution of the polishing pad and generating a measurement signal dependent on the surface constitution of the polishing pad. The measurement signal is compared with corresponding reference values for the purpose of identifying a change in the material of the surface of the substrate during the CMP polishing method.

    摘要翻译: 本发明涉及一种用于监测CMP抛光方法的方法,一种固定在底座中的基板,一个固定在板上的抛光垫,该抛光垫的表面可操作地连接到该基板的表面,该抛光垫和 衬底相对于彼此移动,使得材料从衬底的表面移除。 提供测量装置,其可操作地连接到抛光垫的表面,测量装置检测抛光垫的表面结构,并产生取决于抛光垫的表面结构的测量信号。 将测量信号与相应的参考值进行比较,以便在CMP抛光方法中识别基板表面的材料的变化。

    Process for producing and removing a mask layer
    2.
    发明授权
    Process for producing and removing a mask layer 有权
    掩模层的制造和除去方法

    公开(公告)号:US07129173B2

    公开(公告)日:2006-10-31

    申请号:US10649411

    申请日:2003-08-27

    IPC分类号: H01L21/302

    摘要: A semiconductor substrate is provided, on which there is arranged a first layer, a second layer and a third layer. The third layer is, for example, a resist mask that is used to pattern the second layer. The second layer is, for example, a patterned hard mask used to pattern the first layer. Then, the third layer is removed and a fourth layer is deposited. The fourth layer is, for example, an insulator that fills the trenches which have been formed in the first layer. Then, the fourth layer is planarized by a CMP step. The planarization is continued and the second layer, which is, for example, a hard mask, is removed from the first layer together with the fourth layer. The fourth layer remains in place in a trench which is arranged in the first layer.

    摘要翻译: 提供半导体衬底,其上布置有第一层,第二层和第三层。 第三层例如是用于图案化第二层的抗蚀剂掩模。 第二层例如是用于图案化第一层的图案化硬掩模。 然后,去除第三层,并沉积第四层。 第四层例如是填充已经形成在第一层中的沟槽的绝缘体。 然后,通过CMP步骤对第四层进行平面化。 继续进行平面化,并且第二层(例如硬掩模)与第四层一起从第一层去除。 第四层保持在布置在第一层中的沟槽中的适当位置。