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    Process for producing and removing a mask layer
    1.
    发明授权
    Process for producing and removing a mask layer 有权
    掩模层的制造和除去方法

    公开(公告)号：US07129173B2

    公开(公告)日：2006-10-31

    申请号：US10649411

    申请日：2003-08-27

    申请人： Heike Drummer ,  Franz Kreupl ,  Annette Sänger ,  Manfred Engelhardt ,  Bernhard Sell ,  Peter Thieme

    发明人： Heike Drummer ,  Franz Kreupl ,  Annette Sänger ,  Manfred Engelhardt ,  Bernhard Sell ,  Peter Thieme

    IPC分类号： H01L21/302

    CPC分类号： H01L21/31053 ,  H01L21/30625 ,  H01L21/31144 ,  H01L21/76819

    摘要： A semiconductor substrate is provided, on which there is arranged a first layer, a second layer and a third layer. The third layer is, for example, a resist mask that is used to pattern the second layer. The second layer is, for example, a patterned hard mask used to pattern the first layer. Then, the third layer is removed and a fourth layer is deposited. The fourth layer is, for example, an insulator that fills the trenches which have been formed in the first layer. Then, the fourth layer is planarized by a CMP step. The planarization is continued and the second layer, which is, for example, a hard mask, is removed from the first layer together with the fourth layer. The fourth layer remains in place in a trench which is arranged in the first layer.

    摘要翻译： 提供半导体衬底，其上布置有第一层，第二层和第三层。 第三层例如是用于图案化第二层的抗蚀剂掩模。 第二层例如是用于图案化第一层的图案化硬掩模。 然后，去除第三层，并沉积第四层。 第四层例如是填充已经形成在第一层中的沟槽的绝缘体。 然后，通过CMP步骤对第四层进行平面化。 继续进行平面化，并且第二层（例如硬掩模）与第四层一起从第一层去除。 第四层保持在布置在第一层中的沟槽中的适当位置。

    Patterning of content areas in multilayer metalization configurations of semiconductor components
    3.
    发明授权
    Patterning of content areas in multilayer metalization configurations of semiconductor components 有权
    半导体部件的多层金属化构造中的内容区域的图案化

    公开(公告)号：US06559547B1

    公开(公告)日：2003-05-06

    申请号：US09663569

    申请日：2000-09-15

    申请人： Matthias Uwe Lehr ,  Albrecht Kieslich ,  Peter Thieme ,  Lars Voland

    发明人： Matthias Uwe Lehr ,  Albrecht Kieslich ,  Peter Thieme ,  Lars Voland

    IPC分类号： H01L2348

    CPC分类号： H01L23/528 ,  H01L21/31053 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The semiconductor structure has a layer structure formed from a metalization layer and a dielectric layer. The metalization layer is patterned and has contact areas. The dielectric layer is composed of a depositable material and covers the metalization layer. The contact areas are formed from many contiguous individual structures, which are so narrow that the depositable material does not form, over the individual structures, any areas which run parallel to the metalization layer. The grid of contiguous individual structures forms a contact area which causes dielectric layer elevations which are particularly low and therefore easy to planarize.

    摘要翻译： 半导体结构具有由金属化层和电介质层形成的层结构。 金属化层被图案化并具有接触区域。 电介质层由可沉积材料构成并覆盖金属化层。 接触区域由许多连续的单独结构形成，这些结构非常窄，使得可沉积材料在单个结构上不形成平行于金属化层延伸的任何区域。 连续的单独结构的网格形成接触区域，其导致电介质层的高度特别低，因此易于平坦化。