利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

114 条记录 (耗时 0.03 秒)

    Process for producing and removing a mask layer
    1.
    发明授权
    Process for producing and removing a mask layer 有权
    掩模层的制造和除去方法

    公开(公告)号：US07129173B2

    公开(公告)日：2006-10-31

    申请号：US10649411

    申请日：2003-08-27

    申请人： Heike Drummer ,  Franz Kreupl ,  Annette Sänger ,  Manfred Engelhardt ,  Bernhard Sell ,  Peter Thieme

    发明人： Heike Drummer ,  Franz Kreupl ,  Annette Sänger ,  Manfred Engelhardt ,  Bernhard Sell ,  Peter Thieme

    IPC分类号： H01L21/302

    CPC分类号： H01L21/31053 ,  H01L21/30625 ,  H01L21/31144 ,  H01L21/76819

    摘要： A semiconductor substrate is provided, on which there is arranged a first layer, a second layer and a third layer. The third layer is, for example, a resist mask that is used to pattern the second layer. The second layer is, for example, a patterned hard mask used to pattern the first layer. Then, the third layer is removed and a fourth layer is deposited. The fourth layer is, for example, an insulator that fills the trenches which have been formed in the first layer. Then, the fourth layer is planarized by a CMP step. The planarization is continued and the second layer, which is, for example, a hard mask, is removed from the first layer together with the fourth layer. The fourth layer remains in place in a trench which is arranged in the first layer.

    摘要翻译： 提供半导体衬底，其上布置有第一层，第二层和第三层。 第三层例如是用于图案化第二层的抗蚀剂掩模。 第二层例如是用于图案化第一层的图案化硬掩模。 然后，去除第三层，并沉积第四层。 第四层例如是填充已经形成在第一层中的沟槽的绝缘体。 然后，通过CMP步骤对第四层进行平面化。 继续进行平面化，并且第二层（例如硬掩模）与第四层一起从第一层去除。 第四层保持在布置在第一层中的沟槽中的适当位置。

    Method for fabricating a semiconductor memory component
    2.
    发明授权
    Method for fabricating a semiconductor memory component 有权

    公开(公告)号：US06566220B2

    公开(公告)日：2003-05-20

    申请号：US10013234

    申请日：2001-12-10

    申请人： Manfred Engelhardt ,  Volker Weinrich ,  Franz Kreupl ,  Manuela Schiele

    发明人： Manfred Engelhardt ,  Volker Weinrich ,  Franz Kreupl ,  Manuela Schiele

    IPC分类号： H01L2992

    CPC分类号： H01L28/75 ,  H01L27/10852 ,  H01L28/55

    摘要： The invention relates to a method for fabricating a semiconductor memory component, in particular a DRAM or FeRAM having a silicon substrate. The lower electrode of a storage capacitor is insulated from the silicon substrate by a barrier layer. The barrier layer is patterned using a hard mask, in particular, made from SiO2, SiN, SiON, before the storage capacitor is applied, and the mask layer which remains after the patterning is removed so as to uncover the patterned barrier layer. The invention provides for the patterned barrier layer to be embedded in SiO2 by means of CVD (chemical vapor deposition) prior to the removal of the remaining mask layer, and for the remaining mask layer, together with the SiO2 embedding, to be removed from the surface of the barrier layer using an SiO2-CMP (chemical mechanical polishing) process.

    Method for producing an integrated circuit having at least one metalicized surface
    4.
    发明授权
    Method for producing an integrated circuit having at least one metalicized surface 失效
    一种具有至少一个金属化表面的集成电路的制造方法

    公开(公告)号：US06930052B2

    公开(公告)日：2005-08-16

    申请号：US10654054

    申请日：2003-09-03

    申请人： Siegfried Schwarzl ,  Manfred Engelhardt ,  Franz Kreupl

    发明人： Siegfried Schwarzl ,  Manfred Engelhardt ,  Franz Kreupl

    IPC分类号： H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L21/308

    CPC分类号： H01L21/76807 ,  H01L21/31144 ,  H01L21/76813

    摘要： In order to fabricate a metallization plane with lines and contacts, four dielectric layers are applied to a substrate. Firstly, contact holes are etched through the top two dielectric layers into the underlying dielectric layer, the remaining thickness of the latter layer being essentially equal to the thickness of the top layer. Line trenches are subsequently etched selectively with respect to the first dielectric layer and the third dielectric layer, whose surfaces are uncovered essentially simultaneously. After the first dielectric layer and the third dielectric layer have been patterned, contacts and lines are produced in the contact holes and line trenches.

    摘要翻译： 为了制造具有线和触点的金属化平面，将四个电介质层施加到衬底。 首先，通过顶部的两个电介质层将接触孔蚀刻到下面的介电层中，后一层的剩余厚度基本上等于顶层的厚度。 随后相对于第一电介质层和第三电介质层选择性地蚀刻线沟槽，第三电介质层的表面基本上同时被覆盖。 在第一介电层和第三介质层已被图案化之后，在接触孔和线沟槽中产生接触和线。

    Resistive memory devices with improved resistive changing elements
    5.
    发明授权
    Resistive memory devices with improved resistive changing elements 有权
    具有改进的电阻变化元件的电阻式存储器件

    公开(公告)号：US08742387B2

    公开(公告)日：2014-06-03

    申请号：US12145608

    申请日：2008-06-25

    申请人： Thomas Happ ,  Franz Kreupl ,  Jan Boris Philipp ,  Petra Majewski

    发明人： Thomas Happ ,  Franz Kreupl ,  Jan Boris Philipp ,  Petra Majewski

    IPC分类号： H01L47/00 ,  H01L45/00

    CPC分类号： H01L45/1253 ,  G11C13/0004 ,  G11C2213/79 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/141 ,  H01L45/146

    摘要： An integrated circuit includes a memory cell with a resistance changing memory element. The resistance changing memory element includes a first electrode, a second electrode, and a resistivity changing material disposed between the first and second electrodes, where the resistivity changing material is configured to change resistive states in response to application of a voltage or current to the first and second electrodes. In addition, at least one of the first electrode and the second electrode comprises an insulator material including a self-assembled electrically conductive element formed within the insulator material. The self-assembled electrically conductive element formed within the insulator material remains stable throughout the operation of switching the resistivity changing material to different resistive states.

    摘要翻译： 集成电路包括具有电阻变化存储元件的存储单元。 电阻变化存储元件包括第一电极，第二电极和设置在第一和第二电极之间的电阻率变化材料，其中电阻率变化材料被配置为响应于施加电压或电流而改变电阻状态 和第二电极。 此外，第一电极和第二电极中的至少一个包括绝缘体材料，其包括形成在绝缘体材料内的自组装导电元件。 形成在绝缘体材料内的自组装导电元件在将电阻率变化材料切换到不同电阻状态的整个操作期间保持稳定。

    P-/METAL FLOATING GATE NON-VOLATILE STORAGE ELEMENT
    6.
    发明申请
    P-/METAL FLOATING GATE NON-VOLATILE STORAGE ELEMENT 有权
    P- /金属浮动门非易失存储元件

    公开(公告)号：US20120243337A1

    公开(公告)日：2012-09-27

    申请号：US13153964

    申请日：2011-06-06

    申请人： Sanghyun Lee ,  Mohan Dunga ,  Masaaki Higashitani ,  Tuan Pham ,  Franz Kreupl

    发明人： Sanghyun Lee ,  Mohan Dunga ,  Masaaki Higashitani ,  Tuan Pham ,  Franz Kreupl

    IPC分类号： G11C16/10 ,  G11C16/04 ,  H01L21/336 ,  H01L29/788

    CPC分类号： H01L21/28273 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/42324

    摘要： Non-volatile storage elements having a P−/metal floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have a metal region near the control gate. A P− region near the tunnel oxide helps provide good data retention. A metal region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also, erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.

    摘要翻译： 本文公开了具有P- /金属浮动栅极的非易失性存储元件。 浮栅可以在隧道氧化物附近具有P-区域，并且可以在控制栅极附近具有金属区域。 隧道氧化物附近的P-区域有助于提供良好的数据保留。 控制栅极附近的金属区域有助于实现控制栅极和浮动栅极之间良好的耦合比。 因此，非易失性存储元件的编程是有效的。 此外，擦除非易失性存储元件可能是有效的。 在一些实施例中，在隧道氧化物附近具有P-区（与强掺杂p型半导体相反）可提高相对于P +的擦除效率。

    Memory Cell With Resistance-Switching Layers Including Breakdown Layer
    8.
    发明申请
    Memory Cell With Resistance-Switching Layers Including Breakdown Layer 有权
    具有包含故障层的电阻切换层的存储单元

    公开(公告)号：US20110310656A1

    公开(公告)日：2011-12-22

    申请号：US13157208

    申请日：2011-06-09

    申请人： Franz Kreupl ,  Chu-Chen Fu ,  Yibo Nian

    发明人： Franz Kreupl ,  Chu-Chen Fu ,  Yibo Nian

    IPC分类号： G11C11/00 ,  H01L45/00

    CPC分类号： H01L27/2409 ,  G11C11/16 ,  G11C11/1659 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146

    摘要： A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has a resistance-switching layer, a conductive intermediate layer, and first and second electrodes at either end of the RSME. A breakdown layer is electrically between, and in series with, the second electrode and the intermediate layer. The breakdown layer maintains a resistance of at least about 1-10 MΩ while in a conductive state. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.

    摘要翻译： 3-D读写存储器中的存储器件包括存储器单元。 每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME具有电阻切换层，导电中间层以及在RSME的任一端的第一和第二电极。 击穿层在第二电极和中间层之间电连接并与其串联。 击穿层保持至少约1-10MΩ的电阻; 而处于导电状态。 在存储单元的置位或复位操作中，离子电流在电阻切换层中流动，有助于切换机构。 由于导电中间层的散射，对切换机构无贡献的电子流减少，以避免损坏转向元件。 提供了用于RSME不同层的材料和材料的组合。