Cache memory and cache memory control unit
    1.
    发明授权
    Cache memory and cache memory control unit 有权
    缓存内存和缓存内存控制单元

    公开(公告)号:US09535841B2

    公开(公告)日:2017-01-03

    申请号:US13515315

    申请日:2010-12-14

    IPC分类号: G06F13/00 G06F12/08

    摘要: Data transfer between processors is efficiently performed in a multiprocessor including a shared cache memory. Each entry in a tag storage section 220 of a cache memory holds a reference number field 224 in addition to a tag address field 221, a valid field 222, and a dirty field 223. The reference number field 224 is set in a data write, and the value thereof is decremented after each read access. When the value of the reference number field 224 is changed from “1” to “0”, the entry is invalidated without performing a write-back operation. When the cache memory is used for communication between processors in the multiprocessor system, the cache memory functions as a shared FIFO, and used data is automatically deleted.

    摘要翻译: 在包括共享高速缓冲存储器的多处理器中有效地执行处理器之间的数据传输。 除了标签地址字段221,有效字段222和脏字段223之外,高速缓冲存储器的标签存储部分220中的每个条目保存参考数字段224.参考号字段224被设置在数据写入中, 并且其值在每次读取访问之后递减。 当参考号字段224的值从“1”改变为“0”时,该条目无效而不执行回写操作。 当高速缓冲存储器用于多处理器系统中的处理器之间的通信时,高速缓冲存储器用作共享FIFO,并且使用的数据被自动删除。

    CACHE MEMORY AND CACHE MEMORY CONTROL UNIT
    2.
    发明申请
    CACHE MEMORY AND CACHE MEMORY CONTROL UNIT 有权
    高速缓存存储器和高速缓存存储器控制单元

    公开(公告)号:US20120331234A1

    公开(公告)日:2012-12-27

    申请号:US13515315

    申请日:2010-12-14

    IPC分类号: G06F12/08

    摘要: Data transfer between processors is efficiently performed in a multiprocessor including a shared cache memory. Each entry in a tag storage section 220 of a cache memory holds a reference number field 224 in addition to a tag address field 221, a valid field 222, and a dirty field 223. The reference number field 224 is set in a data write, and the value thereof is decremented after each read access. When the value of the reference number field 224 is changed from “1” to “0”, the entry is invalidated without performing a write-back operation. When the cache memory is used for communication between processors in the multiprocessor system, the cache memory functions as a shared FIFO, and used data is automatically deleted.

    摘要翻译: 在包括共享高速缓冲存储器的多处理器中有效地执行处理器之间的数据传输。 除了标签地址字段221,有效字段222和脏字段223之外,高速缓冲存储器的标签存储部分220中的每个条目保存参考数字段224.参考号字段224被设置在数据写入中, 并且其值在每次读取访问之后递减。 当参考号字段224的值从1变为0时,该条目无效而不执行回写操作。 当高速缓冲存储器用于多处理器系统中的处理器之间的通信时,高速缓冲存储器用作共享FIFO,并且使用的数据被自动删除。

    Floating-point number arithmetic circuit
    3.
    发明申请
    Floating-point number arithmetic circuit 有权
    浮点数运算电路

    公开(公告)号:US20060112160A1

    公开(公告)日:2006-05-25

    申请号:US11280244

    申请日:2005-11-17

    IPC分类号: G06F7/38

    摘要: Disclosed herein is a floating-point number arithmetic circuit for efficiently supplying data to be performed arithmetic operation. The floating-point number arithmetic circuit includes an floating-point number arithmetic unit for performing a predetermined floating-point number arithmetic operation on a floating-point number of a predetermined precision, and a converting circuit for converting data into the floating-point number of predetermined precision and supplying the floating-point number of the predetermined precision to at least either one of input terminals of the floating-point number arithmetic unit.

    摘要翻译: 这里公开了一种用于有效地提供要进行的算术运算的数据的浮点数运算电路。 浮点数算术电路包括用于对预定精度的浮点数执行预定的浮点数算术运算的浮点数运算单元和用于将数据转换为浮点数运算的浮点数运算单元 预定精度,并将预定精度的浮点数提供给浮点数运算单元的输入端中的至少一个。

    Floating-point number arithmetic circuit for handling immediate values
    4.
    发明授权
    Floating-point number arithmetic circuit for handling immediate values 有权
    用于处理立即值的浮点数算术电路

    公开(公告)号:US07949696B2

    公开(公告)日:2011-05-24

    申请号:US11280244

    申请日:2005-11-17

    IPC分类号: G06F7/00 G06F7/38 G06F9/30

    摘要: Disclosed herein is a floating-point number arithmetic circuit for efficiently supplying data to be performed arithmetic operation. The floating-point number arithmetic circuit includes an floating-point number arithmetic unit for performing a predetermined floating-point number arithmetic operation on a floating-point number of a predetermined precision, and a converting circuit for converting data into the floating-point number of predetermined precision and supplying the floating-point number of the predetermined precision to at least either one of input terminals of the floating-point number arithmetic unit.

    摘要翻译: 这里公开了一种用于有效地提供要进行的算术运算的数据的浮点数运算电路。 浮点数算术电路包括用于对预定精度的浮点数执行预定的浮点数算术运算的浮点数运算单元和用于将数据转换为浮点数运算的浮点数运算单元 预定精度,并将预定精度的浮点数提供给浮点数运算单元的输入端中的至少一个。

    Hole examining device
    5.
    发明授权
    Hole examining device 有权
    孔检装置

    公开(公告)号:US09212881B2

    公开(公告)日:2015-12-15

    申请号:US13878511

    申请日:2011-11-08

    摘要: In a hole examining device, an examination head (105) is supported to be movable in an X direction and a Y direction which are orthogonal to each other, measurement heads (125, 126) are supported to be movable in a Z direction which is orthogonal to the X direction and the Y direction with respect to the examination head (105), and a plurality of first measurers (127) and a plurality of second measurers (128) are arranged in the measurement heads (125, 126) in parallel and may be held at an advance position which advances as well as retreats with respect to the Z direction, thereby improving workability of an examining operation.

    摘要翻译: 在检查装置中,检查头(105)被支撑为能够相互正交的X方向和Y方向移动,测量头(125,126)被支撑为能够沿Z方向移动 相对于检查头(105)与X方向和Y方向正交,多个第一测量器(127)和多个第二测量器(128)并联布置在测量头(125,126)中 并且可以保持在相对于Z方向前进并退避的提前位置,从而提高检查操作的可操作性。

    HOLE EXAMINING DEVICE
    7.
    发明申请
    HOLE EXAMINING DEVICE 有权
    孔检测装置

    公开(公告)号:US20130192076A1

    公开(公告)日:2013-08-01

    申请号:US13878511

    申请日:2011-11-08

    IPC分类号: G01B3/00

    摘要: In a hole examining device, an examination head (105) is supported to be movable in an X direction and a Y direction which are orthogonal to each other, measurement heads (125, 126) are supported to be movable in a Z direction which is orthogonal to the X direction and the Y direction with respect to the examination head (105), and a plurality of first measurers (127) and a plurality of second measurers (128) are arranged in the measurement heads (125, 126) in parallel and may be held at an advance position which advances as well as retreats with respect to the Z direction, thereby improving workability of an examining operation.

    摘要翻译: 在检查装置中,检查头(105)被支撑为能够相互正交的X方向和Y方向移动,测量头(125,126)被支撑为能够沿Z方向移动 相对于检查头(105)与X方向和Y方向正交,多个第一测量器(127)和多个第二测量器(128)并联布置在测量头(125,126)中 并且可以保持在相对于Z方向前进并退避的提前位置,从而提高检查操作的可操作性。

    PROCESSOR
    8.
    发明申请
    PROCESSOR 有权
    处理器

    公开(公告)号:US20100011195A1

    公开(公告)日:2010-01-14

    申请号:US12498536

    申请日:2009-07-07

    申请人: Masaaki Ishii

    发明人: Masaaki Ishii

    IPC分类号: G06F9/38

    摘要: A processor includes a plurality of executing sections configured to simultaneously execute instructions for a plurality of threads, an instruction issuing section configured to issue instructions to the plurality of executing sections, and an instruction sync monitoring section configured to, when an instruction-synchronizing instruction is issued to one or more of the plurality of executing sections from the instruction issuing section, monitor completion of execution of the instruction-synchronizing instruction for each of the executing sections, to which the instruction-synchronizing instruction has been issued, thus detecting completion of execution of preceding instructions for the thread to which the instruction-synchronizing instruction belongs. After issuing the instruction-synchronizing instruction, the instruction issuing section stops issuance of succeeding instructions for the thread to which the instruction-synchronizing instruction belongs, until the completion of execution of the preceding instructions for the thread to which the instruction-synchronizing instruction belongs is detected by the instruction sync monitoring section.

    摘要翻译: 处理器包括:多个执行部,被配置为同时执行多个线程的指令;指令发布部,被配置为向多个执行部发出指令;指令同步监视部,被配置为当指令同步指令为 从指令发布部分发出到多个执行部分中的一个或多个执行部分,监视对已经发出指令同步指令的每个执行部分的指令同步指令的执行完成,从而检测执行完成 对于指令同步指令所属的线程的先前指令。 在发出指令同步指令之后,指令发布部分停止向指令同步指令所属的线程发出后续指令,直到对指令同步指令所属的线程的前一条指令的执行完成为止 由指令同步监视部分检测。

    Transfer molding machine for encapsulation of semiconductor devices
    9.
    发明授权
    Transfer molding machine for encapsulation of semiconductor devices 失效
    用于封装半导体器件的转移成型机

    公开(公告)号:US5626886A

    公开(公告)日:1997-05-06

    申请号:US391024

    申请日:1995-02-21

    申请人: Masaaki Ishii

    发明人: Masaaki Ishii

    IPC分类号: B29C45/17 B30B1/10 B29C45/14

    CPC分类号: B29C45/1744 B30B1/103

    摘要: A transfer molding machine for encapsulation of semiconductor devices with a resin comprises a clamping mechanism with an electrically actuated toggle mechanism, a pair of upper and lower sections of a transfer mold, and at least one compensation unit including upper and lower plates and a plurality of elastic members held between said upper and lower plates. The compensation unit is arranged either between the upper stationary platen and the upper mold section or between the moving platen and the lower mold section to compensate the dimensional errors in the mold sections and clamping mechanism.

    摘要翻译: 用于用树脂封装半导体器件的传送成型机包括具有电致动肘节机构的夹紧机构,传递模具的一对上部和下部,以及包括上板和下板的至少一个补偿单元和多个 弹性构件保持在所述上板和下板之间。 补偿单元设置在上固定台板和上模具部分之间或者在移动压板和下模具部分之间,以补偿模具部分和夹紧机构中的尺寸误差。

    Laser recording apparatus
    10.
    发明授权
    Laser recording apparatus 失效
    激光记录装置

    公开(公告)号:US4297713A

    公开(公告)日:1981-10-27

    申请号:US43246

    申请日:1979-05-29

    摘要: A laser recording apparatus includes a laser optical unit having an integral combination of a laser for emitting a laser beam and an optical system for converting the laser beam into an expanded and collimated beam; a deflector unit for directly receiving the laser beam emergent from the laser optical unit and directing the laser beam toward a recording medium; a photoreceptor unit having an integral combination of a reflecting member for reflecting the laser beam deflected by the deflector unit and a photoreceptor for receiving the laser beam reflected by the reflecting member; a support member having standard portions respectively for mounting the laser optical unit, the deflector unit and the photoreceptor unit.

    摘要翻译: 激光记录装置包括具有用于发射激光束的激光器和用于将激光束转换成扩展和准直光束的光学系统的整体组合的激光光学单元; 偏转器单元,用于直接接收来自激光光学单元的激光束并将激光束引向记录介质; 感光单元,其具有用于反射由偏转器单元偏转的激光束的反射构件和用于接收由反射构件反射的激光束的感光体的整体组合; 具有分别用于安装激光光学单元,偏转器单元和感光体单元的标准部分的支撑构件。