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    Method for producing electrolyte solution for lithium ion battery and battery using same
    1.
    发明授权
    Method for producing electrolyte solution for lithium ion battery and battery using same 有权
    锂离子电池用电解液的制造方法及其使用方法

    公开(公告)号：US08097360B2

    公开(公告)日：2012-01-17

    申请号：US11911901

    申请日：2006-04-10

    申请人： Meguru Oe ,  Keiji Sato ,  Hiroaki Sakaguchi

    发明人： Meguru Oe ,  Keiji Sato ,  Hiroaki Sakaguchi

    IPC分类号： H01M6/04

    CPC分类号： H01M10/0568 ,  C01D15/005 ,  H01M10/0525 ,  H01M10/0569 ,  H01M2300/0025

    摘要： A method for producing an electrolyte solution for a lithium ion battery involving reacting a lithium halide selected from the group consisting of lithium fluoride, lithium chloride, lithium bromide, lithium iodide and a mixture of at least two of these, with phosphorus pentachloride and hydrogen fluoride in a nonaqueous organic solvent, thereby producing lithium hexafluorophosphate as an electrolyte of the electrolyte solution.

    摘要翻译： 一种锂离子电池用电解液的制造方法，其特征在于，使选自由氟化锂，氯化锂，溴化锂，碘化锂及其中的至少两种的混合物构成的组中的卤化锂与五氯化磷和氟化氢反应 在非水有机溶剂中，由此生产六氟磷酸锂作为电解质溶液的电解质。

    Interconnection apparatus and controlling method therefor
    3.
    发明授权
    Interconnection apparatus and controlling method therefor 有权
    互连装置及其控制方法

    公开(公告)号：US08732377B2

    公开(公告)日：2014-05-20

    申请号：US13296846

    申请日：2011-11-15

    申请人： Hiroaki Sakaguchi ,  Hitoshi Kai ,  Hiroshi Kobayashi

    发明人： Hiroaki Sakaguchi ,  Hitoshi Kai ,  Hiroshi Kobayashi

    IPC分类号： G06F13/372

    CPC分类号： G06F13/4059 ,  G06F2213/0038

    摘要： Certain aspects of an apparatus and method for interconnection may include an interconnection section, a request processing section and a response processing section. The interconnection section may be configured to transfer a request from a master interface bus to a slave interface bus and to transfer a response from the slave interface bus to the master interface bus. A slot number within the request specifies a time slot during which the interconnection section may be permitted to transfer the response to the master interface bus. The request commands the processing section to load the slot number into a management table. The response commands the response processing section to read out the slot number from the management table.

    摘要翻译： 用于互连的设备和方法的某些方面可以包括互连部分，请求处理部分和响应处理部分。 互连部分可以被配置为将请求从主接口总线传送到从接口总线，并将响应从从接口总线传送到主接口总线。 请求内的时隙号指定可允许互连部分将响应传送到主接口总线的时隙。 请求命令处理部分将插槽号加载到管理表中。 响应命令响应处理部分从管理表中读出插槽号。

    Processor, co-processor, information processing system, and method for controlling processor, co-processor, and information processing system
    4.
    发明申请
    Processor, co-processor, information processing system, and method for controlling processor, co-processor, and information processing system 审中-公开
    处理器，协处理器，信息处理系统以及用于控制处理器，协处理器和信息处理系统的方法

    公开(公告)号：US20110161634A1

    公开(公告)日：2011-06-30

    申请号：US12926350

    申请日：2010-11-12

    申请人： Hiroaki Sakaguchi

    发明人： Hiroaki Sakaguchi

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/30134 ,  G06F9/30145 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3853 ,  G06F9/3877 ,  G06F9/3881

    摘要： A processor includes a buffer that separates a sequence of instructions having no operand into segments and stores the segments, a data holder that holds data to be processed, a decoder that references the data and sequentially decodes at least one of the instructions from the top of the sequence, an instruction execution unit that executes the instruction, and an instruction sequence control unit that controls updating of the instruction sequence in accordance with the decoding result. When the decoded top instruction is a branch instruction and if a branch is taken, the instruction sequence control unit updates the sequence so that the top instruction of one of the segments is located at the top of the sequence. If a branch is not taken, the instruction sequence control unit updates the sequence so that an instruction immediately next to the branch instruction is located at the top of the sequence.

    摘要翻译： 处理器包括一个缓冲器，该缓冲器将没有操作数的指令序列分离成段并存储段，保存要处理数据的数据保持器，引用该数据的解码器，并从至少一个指令从 所述序列，执行所述指令的指令执行单元，以及根据所述解码结果控制所述指令序列的更新的指令序列控制单元。 当解码的顶部指令是分支指令并且如果采用分支时，指令序列控制单元更新该序列，使得其中一个段的顶部指令位于序列的顶部。 如果不采取分支，则指令序列控制单元更新序列，使得紧邻分支指令的指令位于序列的顶部。

    Method of preparing sulfonimide or its salt
    6.
    发明授权
    Method of preparing sulfonimide or its salt 失效
    制备磺酰亚胺或其盐的方法

    公开(公告)号：US5723664A

    公开(公告)日：1998-03-03

    申请号：US525439

    申请日：1995-09-07

    申请人： Hiroaki Sakaguchi ,  Kenji Fujii ,  Shigenori Sakai ,  Yoshiyuki Kobayashi ,  Yasushi Kita

    发明人： Hiroaki Sakaguchi ,  Kenji Fujii ,  Shigenori Sakai ,  Yoshiyuki Kobayashi ,  Yasushi Kita

    IPC分类号： C07C303/38 ,  C07C311/09 ,  C07C311/48 ,  C07D213/20

    CPC分类号： C07D213/20 ,  C07C303/38

    摘要： The invention relates to a method of preparing a sulfonimide, a first salt thereof, or a second salt thereof. The method includes the step of: (a) reacting one or two sulfonyl fluorides with nonhydrous ammonia and an amine component which is one of a tertiary amine and a heterocyclic amine, so as to prepare the first salt. Alternatively, the method includes the step of: (a) reacting the sulfonyl fluoride with the amine component and a sulfonamide, so as to prepare the first salt. The method further optionally includes, after the step (a), the step of: (b) reacting, in an aqueous solution, the first salt with a metal compound, so as to prepare the second salt. The method still further optionally includes, after the step (a), the step of: (c) reacting the first salt with a strong acid so as to prepare the sulfonimide. Alternatively, the method further optionally includes, after the step (b), the step of: (d) reacting the second salt with a strong acid so as to prepare the sulfonimide. The sulfonimide, the first salt or the second salt is easily economically prepared in an industrial scale production with high purity and high yield.

    摘要翻译： 本发明涉及制备磺酰亚胺，其第一种盐或其第二种盐的方法。 所述方法包括以下步骤：（a）使一种或两种磺酰氟与非水氨反应，和作为叔胺和杂环胺之一的胺组分反应，以制备第一种盐。 或者，该方法包括以下步骤：（a）使磺酰氟与胺组分和磺酰胺反应，以制备第一种盐。 该方法进一步任选地包括在步骤（a）之后的步骤：（b）在水溶液中使第一盐与金属化合物反应，以制备第二种盐。 该方法还可任选地在步骤（a）之后包括以下步骤：（c）使第一种盐与强酸反应，以制备磺酰亚胺。 或者，该方法进一步任选地包括在步骤（b）之后的步骤：（d）使第二盐与强酸反应，以制备磺酰亚胺。 磺酰亚胺，第一盐或第二盐在工业规模生产中以高纯度和高产率容易地经济地制备。

    Cache memory and cache memory control unit
    7.
    发明授权
    Cache memory and cache memory control unit 有权
    缓存内存和缓存内存控制单元

    公开(公告)号：US09535841B2

    公开(公告)日：2017-01-03

    申请号：US13515315

    申请日：2010-12-14

    申请人： Taichi Hirao ,  Hiroaki Sakaguchi ,  Hiroshi Yoshikawa ,  Masaaki Ishii

    发明人： Taichi Hirao ,  Hiroaki Sakaguchi ,  Hiroshi Yoshikawa ,  Masaaki Ishii

    IPC分类号： G06F13/00 ,  G06F12/08

    CPC分类号： G06F12/084 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/12 ,  G06F12/128 ,  G06F2212/314 ,  G06F2212/69

    摘要： Data transfer between processors is efficiently performed in a multiprocessor including a shared cache memory. Each entry in a tag storage section 220 of a cache memory holds a reference number field 224 in addition to a tag address field 221, a valid field 222, and a dirty field 223. The reference number field 224 is set in a data write, and the value thereof is decremented after each read access. When the value of the reference number field 224 is changed from “1” to “0”, the entry is invalidated without performing a write-back operation. When the cache memory is used for communication between processors in the multiprocessor system, the cache memory functions as a shared FIFO, and used data is automatically deleted.

    摘要翻译： 在包括共享高速缓冲存储器的多处理器中有效地执行处理器之间的数据传输。 除了标签地址字段221，有效字段222和脏字段223之外，高速缓冲存储器的标签存储部分220中的每个条目保存参考数字段224.参考号字段224被设置在数据写入中， 并且其值在每次读取访问之后递减。 当参考号字段224的值从“1”改变为“0”时，该条目无效而不执行回写操作。 当高速缓冲存储器用于多处理器系统中的处理器之间的通信时，高速缓冲存储器用作共享FIFO，并且使用的数据被自动删除。

    INSTRUCTION FETCH APPARATUS, PROCESSOR AND PROGRAM COUNTER ADDITION CONTROL METHOD
    9.
    发明申请
    INSTRUCTION FETCH APPARATUS, PROCESSOR AND PROGRAM COUNTER ADDITION CONTROL METHOD 有权
    指令设备，处理器和程序计数器附加控制方法

    公开(公告)号：US20110238952A1

    公开(公告)日：2011-09-29

    申请号：US13024580

    申请日：2011-02-10

    申请人： Hitoshi Kai ,  Hiroaki Sakaguchi ,  Hiroshi Kobayashi ,  Katsuhiko Metsugi ,  Haruhisa Yamamoto ,  Yousuke Morita ,  Koichi Hasegawa ,  Taichi Hirao

    发明人： Hitoshi Kai ,  Hiroaki Sakaguchi ,  Hiroshi Kobayashi ,  Katsuhiko Metsugi ,  Haruhisa Yamamoto ,  Yousuke Morita ,  Koichi Hasegawa ,  Taichi Hirao

    IPC分类号： G06F9/38

    CPC分类号： G06F9/321 ,  G06F9/30101 ,  G06F9/30156 ,  G06F9/30167 ,  G06F9/30178 ,  G06F9/3804 ,  G06F9/3842

    摘要： An instruction fetch apparatus is disclosed which includes: a program counter configured to manage the address of an instruction targeted to be executed in a program in which instructions belonging to a plurality of instruction sequences are placed sequentially; a change designation register configured to designate a change of an increment value on the program counter; an increment value register configured to hold the changed increment value; and an addition control section configured such that if the change designation register designates the change of the increment value on the program counter, then the addition control section increments the program counter based on the changed increment value held in the increment value register, the addition control section further incrementing the program counter by an instruction word length if the change designation register does not designate any change of the increment value on the program counter.

    摘要翻译： 一种提取指令装置，其特征在于包括：程序计数器，被配置为在其中顺序放置属于多个指令序列的指令的程序中管理目标要执行的指令的地址; 变更指定寄存器，被配置为指定所述程序计数器上的增量值的变化; 增量值寄存器，被配置为保持所述改变的增量值; 以及附加控制部分，其被配置为使得如果所述改变指定寄存器指定所述程序计数器上的所述增量值的改变，则所述相加控制部分基于所述增量值寄存器中保持的改变的增量值来增加所述程序计数器，所述加法控制 如果改变指定寄存器没有指定程序计数器上的增量值的任何改变，则进一步将程序计数器递增指令字长度。

    Floating-point number arithmetic circuit for handling immediate values
    10.
    发明授权
    Floating-point number arithmetic circuit for handling immediate values 有权
    用于处理立即值的浮点数算术电路

    公开(公告)号：US07949696B2

    公开(公告)日：2011-05-24

    申请号：US11280244

    申请日：2005-11-17

    申请人： Masaaki Ishii ,  Koichi Hasegawa ,  Hiroaki Sakaguchi

    发明人： Masaaki Ishii ,  Koichi Hasegawa ,  Hiroaki Sakaguchi

    IPC分类号： G06F7/00 ,  G06F7/38 ,  G06F9/30

    CPC分类号： G06F9/30029 ,  G06F7/483 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30167 ,  G06F2207/3816 ,  G06F2207/3824

    摘要： Disclosed herein is a floating-point number arithmetic circuit for efficiently supplying data to be performed arithmetic operation. The floating-point number arithmetic circuit includes an floating-point number arithmetic unit for performing a predetermined floating-point number arithmetic operation on a floating-point number of a predetermined precision, and a converting circuit for converting data into the floating-point number of predetermined precision and supplying the floating-point number of the predetermined precision to at least either one of input terminals of the floating-point number arithmetic unit.

    摘要翻译： 这里公开了一种用于有效地提供要进行的算术运算的数据的浮点数运算电路。 浮点数算术电路包括用于对预定精度的浮点数执行预定的浮点数算术运算的浮点数运算单元和用于将数据转换为浮点数运算的浮点数运算单元 预定精度，并将预定精度的浮点数提供给浮点数运算单元的输入端中的至少一个。