公开(公告)号：US5991889A

公开(公告)日：1999-11-23

申请号：US52674

申请日：1998-03-31

申请人： Hiroshi Hikichi ,  Masataka Kimoto

发明人： Hiroshi Hikichi ,  Masataka Kimoto

IPC分类号： G06F12/06 ,  G06F15/78 ,  G11C7/00 ,  G11C7/22 ,  G11C17/00 ,  G06F1/08

CPC分类号： G11C7/22 ,  G11C7/00

摘要： In a microcomputer including a program memory (1) and a CPU (2) operable in one of high-speed and low-speed modes in which the CPU carries out high-speed and low-speed operations when supplied with high-speed and low-speed clock signals (CKH and CKL), respectively, the program memory includes high-speed and low-speed operation memories (11 and 12) for memorizing high-speed and low-speed mode programs which are read by first and second predetermined address ranges of a program address of a program counter (21) of the CPU and which make the CPU carry out the high-speed and the low-speed operations, respectively. A memory controller (3) produces, when detects the second predetermined address range of the program address, a high-speed operation stop signal for stopping operation of the high-speed operation memory. A clock supplying circuit (4) supplies the CPU with one of the high-speed and the low-speed clock signals that corresponds to one of the high-speed and the low-speed modes. The CPU 2 includes an operation mode setting register (22) for setting a different one of the high-speed and the low-speed modes as an operation mode signal (M). In response to the operation mode signal, the clock supplying circuit supplies the CPU 2 with a different one of the high-speed and the low-speed clock signals.

摘要翻译： 在包括程序存储器（1）和CPU（2）的微型计算机中，CPU（2）可以以高速和低速模式中的一种运行，其中CPU在高速和低速模式下执行高速和低速操作 - 速度时钟信号（CKH和CKL），程序存储器包括用于存储由第一和第二预定地址读取的高速和低速模式程序的高速和低速操作存储器（11和12） CPU的程序计数器（21）的程序地址的范围，并且分别使CPU执行高速和低速操作。 存储器控制器（3）当检测到节目地址的第二预定地址范围时产生用于停止高速操作存储器的操作的高速操作停止信号。 时钟供给电路（4）向CPU提供对应于高速和低速模式之一的高速和低速时钟信号之一。 CPU2包括用于将高速和低速模式中的不同的一个设置为操作模式信号（M）的操作模式设置寄存器（22）。 响应于操作模式信号，时钟供应电路为CPU 2提供不同的高速和低速时钟信号。

公开(公告)号：US5459689A

公开(公告)日：1995-10-17

申请号：US686118

申请日：1991-04-15

申请人： Hiroshi Hikichi

发明人： Hiroshi Hikichi

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C7/22 ,  G11C16/06 ,  G11C17/12 ,  G11C7/00

CPC分类号： G11C5/147 ,  G11C17/12 ,  G11C7/22 ,  G11C2207/063

摘要： A memory device has memory cells each of which is addressed according to a timing signal, current sense amplifiers each of which determines whether a current flows in the addressed memory cell or not and reads-out the data stored in such memory cell, a circuit which generates a control signal to become active at a timing when the memory cell Is addressed and to become inactive after the read-out of the stored data is completed by the current sense amplifier, and a circuit which cuts-off based on the control signal a current path of a steady-state current flowing in the current sense amplifier. It is possible to substantially reduce power consumption without sacrificing the capability of the read-out the stored data at a high speed.

摘要翻译： 存储器件具有存储单元，每个存储单元根据定时信号进行寻址，电流检测放大器各自确定电流是否在寻址的存储器单元中流动，并且读出存储在该存储单元中的数据， 在存储单元被寻址的定时产生一个控制信号，以便在当前读出放大器完成对存储的数据的读出之后变为非活动状态，并且基于控制信号a切断一个电路 在电流检测放大器中流动的稳态电流的电流路径。 可以在不牺牲高速读出存储的数据的能力的情况下显着降低功耗。

公开(公告)号：US5694360A

公开(公告)日：1997-12-02

申请号：US589909

申请日：1996-01-23

申请人： Yuichi Iizuka ,  Hiroshi Hikichi

发明人： Yuichi Iizuka ,  Hiroshi Hikichi

IPC分类号： G11C17/00 ,  G06F15/78 ,  G11C16/06 ,  G11C16/10

CPC分类号： G11C16/102

摘要： In a data write apparatus to a flash electrically erasable programmable read only memory (EEPROM) built in a microcomputer which is mounted on a circuit board, a write control section first initializes the flash EEPROM to allow data to be written in the flash EEPROM, and supplies a signal indicative of the data for the flash EEPROM. A level converting section convertes a level of the data signal such that the data signal level matches to an actual operation voltage level of the flash EEPROM and supplies the converted data signal to the flash EEPROM such that the data is written in the flash EEPROM.

摘要翻译： 在安装在电路板上的微型计算机中的闪存电可擦除可编程只读存储器（EEPROM）的数据写入装置中，写入控制部分首先初始化闪速EEPROM以允许将数据写入闪存EEPROM，以及 提供指示闪速EEPROM的数据的信号。 电平转换部分转换数据信号的电平，使得数据信号电平与闪存EEPROM的实际操作电压电平相匹配，并将转换的数据信号提供给快闪EEPROM，使得数据被写入快闪EEPROM。

公开(公告)号：US5254960A

公开(公告)日：1993-10-19

申请号：US928752

申请日：1992-08-13

申请人： Hiroshi Hikichi

发明人： Hiroshi Hikichi

IPC分类号： G06F1/04 ,  G06F15/78 ,  H03K3/013 ,  H03K3/03 ,  H03K5/1252 ,  H03B1/04 ,  H03B5/32 ,  H03K5/01

CPC分类号： H03K3/0307 ,  H03K3/013 ,  H03K5/1252

摘要： A low frequency oscillator circuit to be integrated in a microcomputer for a low consumption power operation with an improved noise resisting performance. The oscillator circuit includes a high frequency clock generator circuit, a shift register for shifting a low frequency signal by the clock, logical AND and OR circuits each receiving the low frequency signal and the output of the shift register, and a flip-flop circuit to be set and reset by the outputs of the logical AND and OR circuits.

摘要翻译： 一种低频振荡电路，集成在微机中，用于具有改进的抗噪声性能的低功耗功率操作。 振荡器电路包括高频时钟发生器电路，用于将低频信号按时钟移位的移位寄存器，每个接收低频信号和移位寄存器的输出的逻辑与和电路以及触发器电路 由逻辑AND和OR电路的输出置1和复位。

公开(公告)号：US4689618A

公开(公告)日：1987-08-25

申请号：US477999

申请日：1983-03-23

申请人： Hiroshi Hikichi

发明人： Hiroshi Hikichi

IPC分类号： G09G3/04

CPC分类号： G09G3/04

摘要： A control circuit for a time division multielement display in which a display information generator provides display information to all elements of the display in common, a digital signal generator enables each of the elements in sequence, an active period control circuit controls the enabling signal of the signal generator, and an active period set circuit sets the length of time the control circuit causes an element to be enabled, whereby erroneous displays due to slow transitions are eliminated by shortening the enabled period.

摘要翻译： 一种用于时分多元显示的控制电路，其中显示信息发生器向显示器的所有元件共同提供显示信息，数字信号发生器使得每个元件都顺序地启用，有源周期控制电路控制 信号发生器，并且有源周期设置电路设置控制电路使得元件能够使能的时间长度，从而通过缩短启用周期来消除由于缓慢转变引起的错误显示。

公开(公告)号：US5453707A

公开(公告)日：1995-09-26

申请号：US178026

申请日：1994-01-06

申请人： Koichi Hiratsuka ,  Hiroshi Hikichi

发明人： Koichi Hiratsuka ,  Hiroshi Hikichi

IPC分类号： H03K5/15 ,  H03K5/151 ,  H03K19/096

CPC分类号： H03K5/1508 ,  H03K5/1515

摘要： A single-phase clock and an output signal of a second delay circuit are inputted to a first NAND gate and a first NOR gate. The output signal of the first NAND gate is inputted to a gate of a first PMOS transistor of a first clock driver. The output signal of the first NOR gate is inputted to a gate of a first NMOS transistor of the first clock driver. Meanwhile, an inverted clock outputted from an inverter and an output signal of a first delay circuit are inputted to a second NAND circuit and a second NOR circuit. The output signal of the second NAND gate is inputted to a gate of a second PMOS transistor of a second clock driver. The output signal of the second NOR gate is inputted to a gate of a second NMOS transistor of the second clock driver.

摘要翻译： 第一延迟电路的单相时钟和输出信号被输入到第一与非门和第一或非门。 第一NAND门的输出信号被输入到第一时钟驱动器的第一PMOS晶体管的栅极。 第一或非门的输出信号被输入到第一时钟驱动器的第一NMOS晶体管的栅极。 同时，从逆变器输出的反相时钟和第一延迟电路的输出信号被输入到第二NAND电路和第二NOR电路。 第二NAND门的输出信号被输入到第二时钟驱动器的第二PMOS晶体管的栅极。 第二或非门的输出信号被输入到第二时钟驱动器的第二NMOS晶体管的栅极。

公开(公告)号：US5914905A

公开(公告)日：1999-06-22

申请号：US964360

申请日：1997-11-04

申请人： Hiroshi Hikichi ,  Yasushi Fukuhara

发明人： Hiroshi Hikichi ,  Yasushi Fukuhara

IPC分类号： G11C29/04 ,  G06F15/78 ,  G11C8/10 ,  G11C29/02 ,  G11C29/34 ,  G11C29/36 ,  G11C29/48 ,  G11C7/00

CPC分类号： G11C8/10 ,  G11C29/34 ,  G11C29/36 ,  G11C29/48

摘要： A semiconductor integrated circuit having a decoder for decoding a first signal supplied thereto and having a plurality of bits and outputting a second signal in which only a predetermined bit of the plurality of bits of the first signal is set at active level, and an internal circuit for, in an ordinary operation mode in which a standby signal is at first level, performing a predetermined processing operation in response to the second signal decoded by said decoder and, in a standby mode in which the standby signal is at second level, stopping the predetermined processing operation to be set in a low power consumption state, comprising a signal level fixing circuit for, when the standby signal is at second level, fixing the predetermined bit of the plurality of bits of the first signal at predetermined level, and supplying a resultant signal to said decoder.

摘要翻译： 一种半导体集成电路，具有：解码器，用于对提供给其的第一信号进行解码，并具有多个位，并输出其中只有第一信号的多个位的预定位被设置为有效电平的第二信号;以及内部电路 在待机信号处于第一电平的普通操作模式中，响应于由所述解码器解码的第二信号执行预定的处理操作，并且在待机信号处于第二电平的待机模式中，停止 预定处理操作被设置在低功耗状态，包括信号电平固定电路，用于当待机信号处于第二电平时，将第一信号的多个位的预定位固定在预定电平，并提供一个 结果信号到所述解码器。

公开(公告)号：US5835706A

公开(公告)日：1998-11-10

申请号：US772770

申请日：1996-12-24

申请人： Hiroshi Hikichi ,  Takashi Igaue

发明人： Hiroshi Hikichi ,  Takashi Igaue

IPC分类号： G06F12/16 ,  G06F1/24 ,  G06F11/07 ,  G06F15/78 ,  G11C16/02 ,  G11C17/00 ,  G06F11/08

CPC分类号： G06F11/073 ,  G06F11/0793

摘要： A user board has an on-board microcomputer including a flash memory and an on-board writing program memory, a user circuit, a reset circuit, a first OR gate, and a second OR gate. A detected signal for resetting the user circuit in an on-board writing mode is supplied from an on-board writing host through the second OR gate to prevent the user circuit from affecting a writing control signal and data to be written into the flash memory.

摘要翻译： 用户板具有车载微型计算机，其包括闪速存储器和车载写入程序存储器，用户电路，复位电路，第一或门和第二或门。 用于通过第二OR门从板上写入主机提供用于在板上写入模式下复位用户电路的检测信号，以防止用户电路影响写入控制信号和要写入闪速存储器的数据。