公开(公告)号：US09383994B2

公开(公告)日：2016-07-05

申请号：US13982526

申请日：2011-09-15

申请人： Toshiki Takeuchi ,  Hiroyuki Igura

发明人： Toshiki Takeuchi ,  Hiroyuki Igura

IPC分类号： G06F9/00 ,  G06F9/30 ,  G06F7/48 ,  G06F9/38 ,  G06F7/57 ,  H04B1/7115

CPC分类号： G06F9/3001 ,  G06F7/4806 ,  G06F7/57 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/3877 ,  H04B1/7115

摘要： In order to enable to quickly and efficiently execute, by one system, various modulation/demodulation/synchronous processes in a plurality of radio communication methods, a co-processor (22) for complex arithmetic processing, which forms a processor system (100), includes a complex arithmetic circuit (22) that executes for complex data a complex arithmetic operation required for radio communication in accordance with an instruction from a primary processor (10), and a memory controller (20, 21) that operates in parallel with the complex arithmetic circuit and accesses a memory. A trace circuit provided in the complex arithmetic circuit (22) monitors arithmetic result data for first complex data series sequentially read from the memory, and detects a normalization coefficient for normalizing the arithmetic result data.

摘要翻译： 为了能够通过一个系统快速有效地执行多个无线电通信方法中的各种调制/解调/同步过程，用于形成处理器系统（100）的用于复杂运算处理的协处理器（22） 包括：复数运算电路（22），用于根据来自主处理器（10）的指令对复数数据执行无线电通信所需的复杂算术运算，以及存储器控制器（20,21），其与所述复合体并行操作 算术电路并访问存储器。 在复数运算电路（22）中提供的跟踪电路监视从存储器顺序读取的第一复数数据序列的运算结果数据，并检测归一化系数以归一化运算结果数据。

公开(公告)号：US08583845B2

公开(公告)日：2013-11-12

申请号：US13054906

申请日：2009-04-22

申请人： Toshiki Takeuchi ,  Hiroyuki Igura

发明人： Toshiki Takeuchi ,  Hiroyuki Igura

IPC分类号： G06F12/00 ,  G06F13/14 ,  G06F13/38

CPC分类号： G06F13/364

摘要： In order to control sub-processors in parallel without losing extensibility, an execution control circuit (30), which forms a multi-processor system (1), issues a process command (CMD) to each of sub-processors (20—1 to 20—3) based on a process sequence (SEQ) designated by a main processor (10), and acquires a process status (STS) which indicates an execution result of processing executed by each of the sub-processors (20—1 to 20—3) in accordance with the process command (CMD). An arbiter circuit (40) arbitrates transfer of the process command (CMD) and the process status (STS) between the execution control circuit (30) and each of the sub-processors (20—1 to 20—3).

摘要翻译： 为了并行地控制子处理器而不损失可扩展性，形成多处理器系统（1）的执行控制电路（30）向每个子处理器（20-1至...）发出处理命令（CMD） 基于由主处理器（10）指定的处理序列（SEQ），并获取指示由每个子处理器执行的处理的执行结果的处理状态（STS）（20-1至20） -3）根据进程命令（CMD）。 仲裁器电路（40）仲裁执行控制电路（30）和每个子处理器（20-1至20-3）之间的处理命令（CMD）和处理状态（STS）的传送。

公开(公告)号：US08341394B2

公开(公告)日：2012-12-25

申请号：US12667156

申请日：2008-07-02

申请人： Toshiki Takeuchi ,  Hiroyuki Igura

发明人： Toshiki Takeuchi ,  Hiroyuki Igura

IPC分类号： H04L29/06

CPC分类号： H04L9/065 ,  H04L2209/122 ,  H04L2209/125

摘要： It is possible to improve a radio communication digital baseband processing device including data encryption/decryption so as to prevent processing failure caused by a data rate increase in recent years by increasing the MAC processing speed of data encryption/decryption and realizing the load distribution in a processing device. A data processing device which performs a communication process including data encryption/decryption includes: a control processor which performs calculation of the MAC processing parameter; and MAC processing means which performs MAC data processing including data encryption/decryption. The control processor controls the MAC processing means by a command script continuously describing a combination of a command and parameter accompanying it.

摘要翻译： 通过增加数据加密/解密的MAC处理速度，实现数据加密/解密的负载分布，可以改善包括数据加密/解密的无线电通信数字基带处理装置，以防止近年来由于数据速率增加引起的处理失败 处理装置。 执行包括数据加密/解密的通信处理的数据处理装置包括：执行MAC处理参数的计算的控制处理器; 以及MAC处理装置，其执行包括数据加密/解密的MAC数据处理。 控制处理器通过连续描述伴随的命令和参数的组合的命令脚本来控制MAC处理装置。

公开(公告)号：US20110289130A1

公开(公告)日：2011-11-24

申请号：US13147738

申请日：2010-02-03

申请人： Hiroyuki Igura

发明人： Hiroyuki Igura

IPC分类号： G06F17/14

CPC分类号： G06F17/142 ,  H04L27/265

摘要： In an FFT computing apparatus, a computation-unit switching detection unit detects timing at which a complex multiplication is not being carried out in said butterfly computation of FFT computation, and a complex-multiplication power-computation unit switches computation between complex multiplication and power computation, based on a detection result by said computation-unit switching detection unit. The complex-multiplication power-computation unit performs power computation at timing at which complex multiplication is not carried out in said butterfly computation of FFT computation.

摘要翻译： 在FFT计算装置中，计算单元切换检测单元在FFT运算的蝶形运算中检测不进行复数乘法的定时，复乘功率计算单元切换复乘法和功率运算之间的运算 基于所述计算单元切换检测单元的检测结果。 复乘功率计算单元在FFT运算的蝶形运算中不执行复数乘法的定时进行功率运算。

公开(公告)号：US20110125948A1

公开(公告)日：2011-05-26

申请号：US13054906

申请日：2009-04-22

申请人： Toshiki Takeuchi ,  Hiroyuki Igura

发明人： Toshiki Takeuchi ,  Hiroyuki Igura

IPC分类号： G06F13/36

CPC分类号： G06F13/364

摘要： In order to control sub-processors in parallel without losing extensibility, an execution control circuit (30), which forms a multi-processor system (1), issues a process command (CMD) to each of sub-processors (20—1 to 20—3) based on a process sequence (SEQ) designated by a main processor (10), and acquires a process status (STS) which indicates an execution result of processing executed by each of the sub-processors (20—1 to 20—3) in accordance with the process command (CMD). An arbiter circuit (40) arbitrates transfer of the process command (CMD) and the process status (STS) between the execution control circuit (30) and each of the sub-processors (20—1 to 20—3).

摘要翻译： 为了并行地控制子处理器而不损失可扩展性，形成多处理器系统（1）的执行控制电路（30）向每个子处理器（20-1至...）发出处理命令（CMD） 基于由主处理器（10）指定的处理序列（SEQ），并获取指示由每个子处理器执行的处理的执行结果的处理状态（STS）（20-1至20） -3）根据进程命令（CMD）。 仲裁器电路（40）仲裁执行控制电路（30）和每个子处理器（20-1至20-3）之间的处理命令（CMD）和处理状态（STS）的传送。

公开(公告)号：US08775750B2

公开(公告)日：2014-07-08

申请号：US13496472

申请日：2009-09-16

申请人： Sheng Wei Chong ,  Hiroyuki Igura

发明人： Sheng Wei Chong ,  Hiroyuki Igura

IPC分类号： G06F12/00 ,  G06F12/06 ,  H03M13/27

CPC分类号： G06F12/0607 ,  H03M13/276 ,  H03M13/6519 ,  H03M13/6561

摘要： An interleaving method includes: generating multiple read-addresses for respective bits of multiple write-words; queuing the read-addresses in parallel in multiple address queues; selecting an address queue among the address queues that is not empty based on status of each address queue; decoding the address from the selected address queue to a read-address and a bit-address; extracting a read-word from data to be interleaved based on the read-address; selecting a write-bit from the read-word based on the bit-address; arbitrating an individual write-bit to one of the write-words based on an address queue ID of the selected address queue; and generating write-addresses for respective write-words.

摘要翻译： 交织方法包括：为多个写入字的各个比特生成多个读取地址; 在多个地址队列中排队读取地址; 根据每个地址队列的状态，选择不为空的地址队列中的地址队列; 将地址从所选地址队列解码为读地址和位地址; 基于读取地址从要交织的数据中提取读取字; 基于位地址从读取字中选择一个写入位; 基于所选择的地址队列的地址队列ID将单独的写入位仲裁到一个写入字; 并为各个写入字生成写地址。

公开(公告)号：US20130322501A1

公开(公告)日：2013-12-05

申请号：US13984792

申请日：2012-02-06

申请人： Toshiki Takeuchi ,  Hiroyuki Igura

发明人： Toshiki Takeuchi ,  Hiroyuki Igura

IPC分类号： H04L1/00

CPC分类号： H04L1/0014 ,  H03M13/09 ,  H03M13/091 ,  H03M13/235 ,  H03M13/2707 ,  H03M13/2732 ,  H03M13/29 ,  H03M13/2957 ,  H03M13/41 ,  H03M13/6513 ,  H03M13/6516 ,  H03M13/6519 ,  H03M13/6561 ,  H04L1/0043 ,  H04L1/0052 ,  H04L1/0071

摘要： An encoding/decoding processor includes a coprocessor that is dedicated to encoding and decoding processes, where the coprocessor comprises: a parameter register that stores externally given operation modes and the settings of generation polynomials; and a calculation circuit that operates on the basis of the operation modes and the generation polynomials and that performs calculations, which are required for the encoding and decoding processes, by a plurality of bits per cycle in a parallel manner, and the coprocessor further comprises memory controllers, which include: address generator circuits for outputting the addresses of the storage devices; FIFO circuits for temporarily storing data; and data packing circuits for making up predetermined numbers of bits of data for output.

摘要翻译： 编码/解码处理器包括专用于编码和解码处理的协处理器，其中协处理器包括：存储外部给定操作模式的参数寄存器和生成多项式的设置; 以及计算电路，其基于操作模式和生成多项式操作，并且以并行方式通过每个周期的多个位执行编码和解码处理所需的计算，并且协处理器还包括存储器 控制器，包括：用于输出存储设备的地址的地址发生器电路; 用于临时存储数据的FIFO电路; 以及用于构成用于输出的预定数量的数据位的数据打包电路。

公开(公告)号：US20100322419A1

公开(公告)日：2010-12-23

申请号：US12667156

申请日：2008-07-02

申请人： Toshiki Takeuchi ,  Hiroyuki Igura

发明人： Toshiki Takeuchi ,  Hiroyuki Igura

IPC分类号： H04L9/00

CPC分类号： H04L9/065 ,  H04L2209/122 ,  H04L2209/125

摘要： It is possible to improve a radio communication digital baseband processing device including data encryption/decryption so as to prevent processing failure caused by a data rate increase in recent years by increasing the MAC processing speed of data encryption/decryption and realizing the load distribution in a processing device. A data processing device which performs a communication process including data encryption/decryption includes: a control processor which performs calculation of the MAC processing parameter; and MAC processing means which performs MAC data processing including data encryption/decryption. The control processor controls the MAC processing means by a command script continuously describing a combination of a command and parameter accompanying it.

摘要翻译： 通过增加数据加密/解密的MAC处理速度，实现数据加密/解密的负载分布，可以改善包括数据加密/解密的无线电通信数字基带处理装置，以防止近年来由于数据速率增加引起的处理失败 处理装置。 执行包括数据加密/解密的通信处理的数据处理装置包括：执行MAC处理参数的计算的控制处理器; 以及MAC处理装置，其执行包括数据加密/解密的MAC数据处理。 控制处理器通过连续描述伴随的命令和参数的组合的命令脚本来控制MAC处理装置。

公开(公告)号：US06205192B1

公开(公告)日：2001-03-20

申请号：US09145262

申请日：1998-09-02

申请人： Hiroyuki Igura

发明人： Hiroyuki Igura

IPC分类号： G06F104

CPC分类号： H03L7/00 ,  H04L7/02 ,  H04L7/0331

摘要： In response to the inputting of an asynchronous signal (DATA) which is not synchronized with a clock signal, the inputting of the clock signal to the inside of the device is controlled to an on-state. Further, in response to the termination of the operation of the device, the inputting of the clock signal to the inside of the device is controlled to an off-state. In this case, the level change of the asynchronous signal is detected by a comparator, and based on the detection result, the inputting of the clock signal is controlled to either the on-state or the off-state by a clock control circuit. By stopping the inputting of the clock signal, the power consumption of the device can be reduced.

摘要翻译： 响应于不与时钟信号同步的异步信号（DATA）的输入，将设备内部的时钟信号的输入控制为接通状态。 此外，响应于设备的操作的终止，将时钟信号输入到设备内部被控制为关闭状态。 在这种情况下，异步信号的电平变化由比较器检测，并且基于检测结果，通过时钟控制电路将时钟信号的输入控制为导通状态或截止状态。 通过停止输入时钟信号，能够降低设备的功耗。

公开(公告)号：US09405549B2

公开(公告)日：2016-08-02

申请号：US14003166

申请日：2011-10-26

申请人： Hiroyuki Igura

发明人： Hiroyuki Igura

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/52

CPC分类号： G06F9/3861 ,  G06F9/524

摘要： A processor core interrupt control circuit issues a request signal for requesting cancellation of a coprocessor instruction being executed at a coprocessor. A program control circuit issues interrupt processing after issuance of the cancellation request. A coprocessor computation control circuit retains the execution state of the coprocessor instruction. Upon receiving the processing cancellation request signal, a coprocessor interrupt control circuit performs cancellation or holding of the coprocessor instruction on the basis of execution state information retained by the coprocessor computation control circuit. The coprocessor interrupt control circuit evicts the execution state of the coprocessor instruction in the case of holding, and restores the execution state of the coprocessor instruction that had been evicted after completion of the interrupt processing.

摘要翻译： 处理器核心中断控制电路发出用于请求取消在协处理器上执行的协处理器指令的请求信号。 程序控制电路在发出取消请求后发出中断处理。 协处理器计算控制电路保持协处理器指令的执行状态。 协处理器中断控制电路在接收到处理取消请求信号时，根据由协处理器运算控制电路保存的执行状态信息，执行协处理器指令的取消或保持。 协处理器中断控制电路在保持时将协处理器指令的执行状态排除，并恢复中断处理完成后被驱逐的协处理器指令的执行状态。