公开(公告)号：US20130056817A1

公开(公告)日：2013-03-07

申请号：US13592822

申请日：2012-08-23

申请人： Daewoong Kim ,  Junkyu Yang ,  HongSuk Kim ,  Tae-Jong Han

发明人： Daewoong Kim ,  Junkyu Yang ,  HongSuk Kim ,  Tae-Jong Han

IPC分类号： H01L27/105

CPC分类号： H01L27/11521 ,  H01L21/764

摘要： Provided are semiconductor devices and methods of forming the same. A device isolation structure in the semiconductor device includes a gap region. A dielectric constant of a vacuum or an air in the gap region is smaller than a dielectric constant of an oxide layer and, as a result coupling and attendant interference between adjacent cells may be reduced.

公开(公告)号：US20120104485A1

公开(公告)日：2012-05-03

申请号：US13281784

申请日：2011-10-26

申请人： Junkyu Yang ,  HongSuk Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  Guk-Hyon Yon

发明人： Junkyu Yang ,  HongSuk Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  Guk-Hyon Yon

IPC分类号： H01L29/792

CPC分类号： H01L27/11521 ,  H01L21/764 ,  H01L27/11568

摘要： A method of manufacturing a nonvolatile memory device includes forming a tunnel dielectric layer, a charge storage layer, and a hard mask layer on a substrate in sequential order. Active portions are defined by forming trenches in the substrate. A tunnel dielectric pattern, a preliminary charge storage pattern, and a hard mask pattern are formed on each of the active portions in sequential order by sequentially patterning the hard mask layer, the charge storage layer, the tunnel dielectric layer, and the substrate. A capping pattern is formed covering an upper surface of the trenches such that a first void remains in a lower portion of the trenches, the capping pattern including etch particles formed by etching the hard mask pattern through a sputtering etch process.

摘要翻译： 一种制造非易失性存储器件的方法包括在衬底上依次形成隧道介电层，电荷存储层和硬掩模层。 通过在衬底中形成沟槽来限定活性部分。 通过对硬掩模层，电荷存储层，隧道介电层和衬底进行顺序构图，按顺序在有源部分的每一个上形成隧道电介质图案，初电电荷存储图案和硬掩模图案。 形成覆盖沟槽的上表面的覆盖图案，使得第一空隙保留在沟槽的下部，封盖图案包括通过溅射蚀刻工艺蚀刻硬掩模图案形成的蚀刻颗粒。

公开(公告)号：US08809937B2

公开(公告)日：2014-08-19

申请号：US13592822

申请日：2012-08-23

申请人： Daewoong Kim ,  Junkyu Yang ,  HongSuk Kim ,  Tae-Jong Han

发明人： Daewoong Kim ,  Junkyu Yang ,  HongSuk Kim ,  Tae-Jong Han

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/764

摘要： Provided are semiconductor devices and methods of forming the same. A device isolation structure in the semiconductor device includes a gap region. A dielectric constant of a vacuum or an air in the gap region is smaller than a dielectric constant of an oxide layer and, as a result coupling and attendant interference between adjacent cells may be reduced.

摘要翻译： 提供半导体器件及其形成方法。 半导体器件中的器件隔离结构包括间隙区域。 间隙区域中的真空或空气的介电常数小于氧化物层的介电常数，结果可能减少相邻电池之间的耦合和伴随的干扰。

公开(公告)号：US20140061757A1

公开(公告)日：2014-03-06

申请号：US13971279

申请日：2013-08-20

申请人： SUNGGIL KIM ,  Sunghoi Hur ,  Jung-Hwan Kim ,  HongSuk Kim ,  Guk-Hyon Yon ,  JaeHo Choi

发明人： SUNGGIL KIM ,  Sunghoi Hur ,  Jung-Hwan Kim ,  HongSuk Kim ,  Guk-Hyon Yon ,  JaeHo Choi

IPC分类号： H01L29/788 ,  H01L29/66

CPC分类号： H01L29/788 ,  H01L21/764 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11582 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

摘要： A semiconductor device includes a semiconductor substrate having a plurality of active regions defined by a trench. A gate electrode crosses the plurality of active regions. A plurality of charge storing cells is disposed between the gate electrode and each of the plurality of active regions. A porous insulating layer is disposed between the gate electrode and the plurality of charge storing cells. The porous insulating layer includes a portion extended over the trench. An air gap is disposed between the extended portion of the porous insulating layer and a bottom surface of the trench.

摘要翻译： 半导体器件包括具有由沟槽限定的多个有源区的半导体衬底。 栅电极与多个有源区交叉。 多个电荷存储单元设置在栅电极和多个有源区域中的每一个之间。 多孔绝缘层设置在栅电极和多个电荷存储单元之间。 多孔绝缘层包括在沟槽上延伸的部分。 空隙设置在多孔绝缘层的延伸部分和沟槽的底表面之间。

公开(公告)号：US20170301689A1

公开(公告)日：2017-10-19

申请号：US15634555

申请日：2017-06-27

申请人： Ji-Hoon CHOI ,  SeungHyun LIM ,  Sunggil KIM ,  HongSuk KIM ,  Hunhyeong LIM ,  Hyunjun SIM

发明人： Ji-Hoon CHOI ,  SeungHyun LIM ,  Sunggil KIM ,  HongSuk KIM ,  Hunhyeong LIM ,  Hyunjun SIM

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

摘要： A semiconductor memory device includes a stack including gate electrodes sequentially stacked on a substrate, a vertical insulating structure penetrating the stack vertically with respect to the gate electrodes, a vertical channel portion disposed on an inner side surface of the vertical insulating structure, and a common source region formed in the substrate and spaced apart from the vertical channel portion. A bottom region of the vertical channel portion has a protruding surface in contact with a bottom region of the vertical insulating structure.

公开(公告)号：US20160276365A1

公开(公告)日：2016-09-22

申请号：US15066619

申请日：2016-03-10

申请人： JI-HOON CHOI ,  SEUNGHYUN LIM ,  SUNGGIL KIM ,  HONGSUK KIM ,  HUNHYEONG LIM ,  HYUNJUN SIM

发明人： JI-HOON CHOI ,  SEUNGHYUN LIM ,  SUNGGIL KIM ,  HONGSUK KIM ,  HUNHYEONG LIM ,  HYUNJUN SIM

IPC分类号： H01L27/115 ,  H01L29/10

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

摘要： A semiconductor memory device includes a stack including gate electrodes sequentially stacked on a substrate, a vertical insulating structure penetrating the stack vertically with respect to the gate electrodes, a vertical channel portion disposed on an inner side surface of the vertical insulating structure, and a common source region formed in the substrate and spaced apart from the vertical channel portion. A bottom region of the vertical channel portion has a protruding surface in contact with a bottom region of the vertical insulating structure.

摘要翻译： 一种半导体存储器件包括：堆叠，其包括依次层叠在基板上的栅极电极，相对于栅电极垂直地贯穿堆叠体的垂直绝缘结构，设置在垂直绝缘结构的内侧面的垂直沟道部， 源极区域形成在衬底中并且与垂直沟道部分间隔开。 垂直通道部分的底部区域具有与垂直绝缘结构的底部区域接触的突出表面。