公开(公告)号：US20120104485A1

公开(公告)日：2012-05-03

申请号：US13281784

申请日：2011-10-26

申请人： Junkyu Yang ,  HongSuk Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  Guk-Hyon Yon

发明人： Junkyu Yang ,  HongSuk Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  Guk-Hyon Yon

IPC分类号： H01L29/792

CPC分类号： H01L27/11521 ,  H01L21/764 ,  H01L27/11568

摘要： A method of manufacturing a nonvolatile memory device includes forming a tunnel dielectric layer, a charge storage layer, and a hard mask layer on a substrate in sequential order. Active portions are defined by forming trenches in the substrate. A tunnel dielectric pattern, a preliminary charge storage pattern, and a hard mask pattern are formed on each of the active portions in sequential order by sequentially patterning the hard mask layer, the charge storage layer, the tunnel dielectric layer, and the substrate. A capping pattern is formed covering an upper surface of the trenches such that a first void remains in a lower portion of the trenches, the capping pattern including etch particles formed by etching the hard mask pattern through a sputtering etch process.

摘要翻译： 一种制造非易失性存储器件的方法包括在衬底上依次形成隧道介电层，电荷存储层和硬掩模层。 通过在衬底中形成沟槽来限定活性部分。 通过对硬掩模层，电荷存储层，隧道介电层和衬底进行顺序构图，按顺序在有源部分的每一个上形成隧道电介质图案，初电电荷存储图案和硬掩模图案。 形成覆盖沟槽的上表面的覆盖图案，使得第一空隙保留在沟槽的下部，封盖图案包括通过溅射蚀刻工艺蚀刻硬掩模图案形成的蚀刻颗粒。

公开(公告)号：US20110049610A1

公开(公告)日：2011-03-03

申请号：US12845375

申请日：2010-07-28

申请人： Junkyu Yang ,  Jaeyoung Ahn ,  Young-Geun Park ,  Kihyun Hwang ,  Dongwoon Shin ,  Juyul Lee

发明人： Junkyu Yang ,  Jaeyoung Ahn ,  Young-Geun Park ,  Kihyun Hwang ,  Dongwoon Shin ,  Juyul Lee

IPC分类号： H01L29/792

CPC分类号： H01L29/513 ,  G11C16/0466 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/792

摘要： Provided are a nonvolatile memory device and a method of forming the same. The nonvolatile memory device includes: a semiconductor substrate including a device isolation layer defining an active region; a tunnel insulating layer on the active region; a charge trapping layer on the tunnel insulating layer; a blocking insulating layer on the charge trapping layer and the device isolation layer; a gate electrode on the blocking insulating layer; and a barrier capping layer formed between the device isolation layer and the blocking insulating layer.

摘要翻译： 提供一种非易失性存储器件及其形成方法。 非易失性存储器件包括：半导体衬底，其包括限定有源区的器件隔离层; 有源区上的隧道绝缘层; 隧道绝缘层上的电荷捕获层; 电荷俘获层和器件隔离层上的阻挡绝缘层; 阻挡绝缘层上的栅电极; 以及在器件隔离层和阻挡绝缘层之间形成的阻挡层覆盖层。

公开(公告)号：US20140035026A1

公开(公告)日：2014-02-06

申请号：US13800872

申请日：2013-03-13

申请人： Byong-hyun Jang ,  Juhyung Kim ,  Woonkyung Lee ,  Jaegoo Lee ,  Chaeho Kim ,  Junkyu Yang ,  Phil Ouk Nam ,  Jaeyoung Ahn ,  Kihyun Hwang

发明人： Byong-hyun Jang ,  Juhyung Kim ,  Woonkyung Lee ,  Jaegoo Lee ,  Chaeho Kim ,  Junkyu Yang ,  Phil Ouk Nam ,  Jaeyoung Ahn ,  Kihyun Hwang

IPC分类号： H01L29/792 ,  H01L29/66

CPC分类号： H01L29/792 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/045 ,  H01L29/1037 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/66833 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.

摘要翻译： 一种半导体存储器件及其制造方法。 该器件包括垂直堆叠在衬底的顶表面上的多个栅极，该衬底的顶表面上形成有在该衬底中形成的外延层，垂直穿过该栅极的垂直沟道以与该外延层电连接;以及存储层，设置在该垂直沟道 和大门。 外延层具有位于最下面一个栅极的底表面和基板的顶表面之间的高度的顶表面。

公开(公告)号：US20130313631A1

公开(公告)日：2013-11-28

申请号：US13828557

申请日：2013-03-14

申请人： Junkyu Yang ,  Phil Ouk Nam ,  Youngseon Son ,  Kwangyoung Lee ,  Kihyun Hwang

发明人： Junkyu Yang ,  Phil Ouk Nam ,  Youngseon Son ,  Kwangyoung Lee ,  Kihyun Hwang

IPC分类号： H01L27/088

CPC分类号： H01L27/088 ,  H01L27/11556 ,  H01L27/11578

摘要： A three-dimensional (3D) nonvolatile memory device includes a vertical stack of nonvolatile memory cells on a substrate having a region of first conductivity type therein. A dopant region of second conductivity type is provided in the substrate. This dopant region forms a P—N rectifying junction with the region of first conductivity type and has a concave upper surface that is recessed relative to an upper surface of the substrate upon which the vertical stack of nonvolatile memory cells extends. An electrically insulating electrode separating pattern is provided, which extends through the vertical stack of nonvolatile memory cells and into the recess in the dopant region of second conductivity type.

摘要翻译： 三维（3D）非易失性存储器件包括在其中具有第一导电类型区域的衬底上的非易失性存储器单元的垂直堆叠。 在基板中设置第二导电类型的掺杂区域。 该掺杂剂区域与第一导电类型的区域形成P-N整流结，并且具有相对于垂直堆叠的非易失性存储单元延伸的衬底的上表面凹陷的凹上表面。 提供电绝缘电极分离图案，其延伸穿过垂直堆叠的非易失性存储单元并进入第二导电类型的掺杂区域中的凹槽中。

公开(公告)号：US20110303971A1

公开(公告)日：2011-12-15

申请号：US13157659

申请日：2011-06-10

申请人： Changwon Lee ,  Kihyun Hwang ,  Hanmei Choi ,  Sun Woo Lee ,  Junkyu Yang ,  Sunggil Kim ,  Jeonggil Lee ,  Seon-Ho Jo

发明人： Changwon Lee ,  Kihyun Hwang ,  Hanmei Choi ,  Sun Woo Lee ,  Junkyu Yang ,  Sunggil Kim ,  Jeonggil Lee ,  Seon-Ho Jo

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A method for manufacturing a three-dimensional semiconductor memory includes forming a plurality of stacked structures disposed on a substrate to be spaced apart from each other, each of the stacked structures including a plurality of dielectric patterns and a plurality of polysilicon patterns alternately stacked, forming a metal layer to cover sidewalls of the stacked structures and a top surface of the substrate exposed between the stacked structures, and forming stacked gate electrodes on the substrate and a conductive line in the substrate by performing a silicidation process between the metal layer and each of the polysilicon patterns and the substrate.

摘要翻译： 一种三维半导体存储器的制造方法，其特征在于，在基板上形成多个层叠结构，使其彼此间隔开，所述堆叠结构中的每一个包括多个电介质图案和多个多晶硅图案，交替层叠，形成 覆盖层叠结构的侧壁的金属层和露出在层叠结构之间的基板的顶面，通过在金属层与金属层之间进行硅化处理，在基板上形成层叠的栅电极和基板的导电线 多晶硅图案和衬底。

公开(公告)号：US20120001345A1

公开(公告)日：2012-01-05

申请号：US13173304

申请日：2011-06-30

申请人： Chanjin Park ,  Kihyun Hwang ,  Dongchul Yoo ,  Junkyu Yang ,  Gyungjin Min ,  Yoochul Kong ,  Hanmei Choi

发明人： Chanjin Park ,  Kihyun Hwang ,  Dongchul Yoo ,  Junkyu Yang ,  Gyungjin Min ,  Yoochul Kong ,  Hanmei Choi

IPC分类号： H01L23/48 ,  H01L21/306 ,  H01L21/768

CPC分类号： H01L29/788 ,  H01L23/5384 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.

摘要翻译： 提供三维半导体器件。 该装置可以包括垂直和顺序堆叠的模具层，堆叠的模具层之间的导电图案，垂直穿过堆叠的模具层的插入图案，导电图案和插入图案之间的中间图案，以及模具层之间的保护层图案 和封堵图案，其中保护层图案由中间图案分离。

公开(公告)号：US08575682B2

公开(公告)日：2013-11-05

申请号：US13323452

申请日：2011-12-12

申请人： Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

发明人： Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

IPC分类号： H01L29/66

CPC分类号： H01L29/66666 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided are three-dimensional semiconductor memory devices and methods of forming the same. The device includes a substrate, conductive patterns stacked on the substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern may include a first doped region provided in an upper portion of the active pattern, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.

摘要翻译： 提供三维半导体存储器件及其形成方法。 该器件包括衬底，堆叠在衬底上的导电图案，以及穿透要连接到衬底的导电图案的有源图案。 有源图案可以包括设置在有源图案的上部的第一掺杂区域和与第一掺杂区域的至少一部分重叠的扩散阻抗掺杂区域。 扩散阻止掺杂区域可以是掺杂有碳的区域。

公开(公告)号：US20120153372A1

公开(公告)日：2012-06-21

申请号：US13323452

申请日：2011-12-12

申请人： Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

发明人： Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

IPC分类号： H01L29/78

CPC分类号： H01L29/66666 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided are three-dimensional semiconductor memory devices and methods of forming the same. The device includes a substrate, conductive patterns stacked on the substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern may include a first doped region provided in an upper portion of the active pattern, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.

摘要翻译： 提供三维半导体存储器件及其形成方法。 该器件包括衬底，堆叠在衬底上的导电图案，以及穿透要连接到衬底的导电图案的有源图案。 有源图案可以包括设置在有源图案的上部的第一掺杂区域和与第一掺杂区域的至少一部分重叠的扩散阻抗掺杂区域。 扩散阻止掺杂区域可以是掺杂有碳的区域。

公开(公告)号：US08952448B2

公开(公告)日：2015-02-10

申请号：US13828557

申请日：2013-03-14

申请人： Junkyu Yang ,  Phil Ouk Nam ,  Youngseon Son ,  Kwangyoung Lee ,  Kihyun Hwang

发明人： Junkyu Yang ,  Phil Ouk Nam ,  Youngseon Son ,  Kwangyoung Lee ,  Kihyun Hwang

IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L27/115

CPC分类号： H01L27/088 ,  H01L27/11556 ,  H01L27/11578

摘要： A three-dimensional (3D) nonvolatile memory device includes a vertical stack of nonvolatile memory cells on a substrate having a region of first conductivity type therein. A dopant region of second conductivity type is provided in the substrate. This dopant region forms a P-N rectifying junction with the region of first conductivity type and has a concave upper surface that is recessed relative to an upper surface of the substrate upon which the vertical stack of nonvolatile memory cells extends. An electrically insulating electrode separating pattern is provided, which extends through the vertical stack of nonvolatile memory cells and into the recess in the dopant region of second conductivity type.

摘要翻译： 三维（3D）非易失性存储器件包括在其中具有第一导电类型区域的衬底上的非易失性存储器单元的垂直堆叠。 在基板中设置第二导电类型的掺杂区域。 该掺杂剂区域与第一导电类型的区域形成P-N整流结，并且具有相对于垂直堆叠的非易失性存储单元延伸的衬底的上表面凹陷的凹上表面。 提供电绝缘电极分离图案，其延伸穿过垂直堆叠的非易失性存储单元并进入第二导电类型的掺杂区域中的凹槽中。

公开(公告)号：US08377817B2

公开(公告)日：2013-02-19

申请号：US13173304

申请日：2011-06-30

申请人： Chanjin Park ,  Kihyun Hwang ,  Dongchul Yoo ,  Junkyu Yang ,  Gyungjin Min ,  Yoochul Kong ,  Hanmei Choi

发明人： Chanjin Park ,  Kihyun Hwang ,  Dongchul Yoo ,  Junkyu Yang ,  Gyungjin Min ,  Yoochul Kong ,  Hanmei Choi

IPC分类号： H01L21/4763

CPC分类号： H01L29/788 ,  H01L23/5384 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.