公开(公告)号：US08507316B2

公开(公告)日：2013-08-13

申请号：US12976437

申请日：2010-12-22

Applicant: Hui-Chen Chu ,  Yian-Liang Kuo

Inventor： Hui-Chen Chu ,  Yian-Liang Kuo

IPC: H01L21/44 ,  H01L21/30 ,  H01L23/48

CPC classification number: H01L27/14618 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L27/14687 ,  H01L2224/13

Abstract: A method includes performing a first die-saw on a package structure includes forming a first and a second metal lead extending into a trench of a package structure, wherein the first and the second metal leads contact the side edges of contact pads that are in devices in the package structure. The first and the second metal leads are interconnected through a connecting metal portion. A pre-cut is performed to cut the connecting metal portion to separate the first and the second metal leads, wherein remaining portions of the connecting metal portion have edges after the pre-cut. A dielectric coating is formed over the first and the second metal leads. A die-saw is performed to saw apart the package structure, so that the first and the second dies are separated into separate piece. In each of the resulting pieces, the edges of the remaining portions of the connecting metal portion are covered by remaining portions of the first dielectric coating.

Abstract translation: 一种方法包括在封装结构上执行第一模锯，包括形成延伸到封装结构的沟槽中的第一和第二金属引线，其中第一和第二金属引线接触设备中的接触焊盘的侧边缘 在包装结构中。 第一和第二金属引线通过连接金属部分相互连接。 执行切割以切割连接金属部分以分离第一和第二金属引线，其中连接金属部分的剩余部分在预切割之后具有边缘。 在第一和第二金属引线上形成电介质涂层。 执行模锯以分离包装结构，使得第一和第二模具被分离成单独的部件。 在每个所得的部件中，连接金属部分的其余部分的边缘被第一电介质涂层的剩余部分覆盖。

公开(公告)号：US6069042A

公开(公告)日：2000-05-30

申请号：US23065

申请日：1998-02-13

Applicant: Wen-Cheng Chien ,  Hui-Chen Chu

Inventor： Wen-Cheng Chien ,  Hui-Chen Chu

IPC: H01L21/336 ,  H01L29/423 ,  H01L21/8247

CPC classification number: H01L29/66825 ,  H01L29/42324

Abstract: A method is provided for forming multi-layer spacer GELS) for flash EEPROM devices. A composite tetraethyl orthosilicate-silicon nitride (TEOS/Si.sub.3 N.sub.4) layer is deposited over the floating gate and anisotropically etched to form the MLS. The resulting MLS is better controlled dimensionally with the attendant advantage, therefore, of better definition of gate and channel lengths in the memory cell for more predictable and better programming and erase performance of EEPROMS.

Abstract translation: 提供了用于形成用于闪存EEPROM器件的多层间隔物GELS的方法。 将复合四乙基原硅酸盐 - 氮化硅（TEOS / Si 3 N 4）层沉积在浮动栅极上并进行各向异性蚀刻以形成MLS。 所得到的MLS在维度上更好地受到控制，因此，存储器单元中门和通道长度的更好的定义可以更好地预测和更好地编程和擦除EEPROMS的性能。

公开(公告)号：US20120161308A1

公开(公告)日：2012-06-28

申请号：US12976437

申请日：2010-12-22

Applicant: Hui-Chen Chu ,  Yian-Liang Kuo

Inventor： Hui-Chen Chu ,  Yian-Liang Kuo

IPC: H01L23/498 ,  H01L31/18 ,  H01L21/78

CPC classification number: H01L27/14618 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L27/14687 ,  H01L2224/13

Abstract: A method includes performing a first die-saw on a package structure includes forming a first and a second metal lead extending into a trench of a package structure, wherein the first and the second metal leads contact the side edges of contact pads that are in devices in the package structure. The first and the second metal leads are interconnected through a connecting metal portion. A pre-cut is performed to cut the connecting metal portion to separate the first and the second metal leads, wherein remaining portions of the connecting metal portion have edges after the pre-cut. A dielectric coating is formed over the first and the second metal leads. A die-saw is performed to saw apart the package structure, so that the first and the second dies are separated into separate piece. In each of the resulting pieces, the edges of the remaining portions of the connecting metal portion are covered by remaining portions of the first dielectric coating.

Abstract translation: 一种方法包括在封装结构上执行第一模锯，包括形成延伸到封装结构的沟槽中的第一和第二金属引线，其中第一和第二金属引线接触设备中的接触焊盘的侧边缘 在包装结构中。 第一和第二金属引线通过连接金属部分相互连接。 执行切割以切割连接金属部分以分离第一和第二金属引线，其中连接金属部分的剩余部分在预切割之后具有边缘。 在第一和第二金属引线上形成电介质涂层。 执行模锯以分离包装结构，使得第一和第二模具被分离成单独的部件。 在每个所得的部件中，连接金属部分的其余部分的边缘被第一电介质涂层的剩余部分覆盖。

公开(公告)号：US06947801B2

公开(公告)日：2005-09-20

申请号：US10639980

申请日：2003-08-13

Applicant: Shui-Tien Lin ,  Hui-Chen Chu ,  Hui-Wen Yang ,  Fu-Ching Yang

Inventor： Shui-Tien Lin ,  Hui-Chen Chu ,  Hui-Wen Yang ,  Fu-Ching Yang

IPC: G05B17/00 ,  G05B19/418 ,  G06F19/00

CPC classification number: G05B19/41865 ,  G05B2219/32191 ,  Y02P90/18 ,  Y02P90/20 ,  Y02P90/22

Abstract: A method system for synchronizing a control chart of an SPC system and equipment performance has a chart model (22) with new chart properties; a method for calculating a control limit based on a statistical deviation, a synchronization frequency for setting a time for reviewing new data gathered by the SPC system, and a process catalog for categorizing all control charts that control the same process step, such that the control charts are organized for assignment of the same performance based control limit calculated by using statistics formed by data for control limit values of the control charts.

Abstract translation: 用于同步SPC系统的控制图和设备性能的方法系统具有具有新图表属性的图表模型（22）; 用于计算基于统计偏差的控制限制的方法，用于设置用于检查由SPC系统收集的新数据的时间的同步频率以及用于对控制相同处理步骤的所有控制图进行分类的处理目录，使得控制 组织图表用于分配通过使用由控制图的控制限制值的数据形成的统计计算的相同基于性能的控制限制。

公开(公告)号：US20050038543A1

公开(公告)日：2005-02-17

申请号：US10639980

申请日：2003-08-13

Applicant: Shui-Tien Lin ,  Hui-Chen Chu ,  Hui-Wen Yang ,  Fu-Ching Yang

Inventor： Shui-Tien Lin ,  Hui-Chen Chu ,  Hui-Wen Yang ,  Fu-Ching Yang

IPC: G05B17/00 ,  G05B19/418 ,  G06F19/00

CPC classification number: G05B19/41865 ,  G05B2219/32191 ,  Y02P90/18 ,  Y02P90/20 ,  Y02P90/22

Abstract: A method and system for synchronizing a control chart of an SPC system and equipment performance has a chart model (22) with new chart properties; a method for calculating a control limit based on a statistical deviation, a synchronization frequency for setting a time for reviewing new data gathered by the SPC system, and a process catalog for categorizing all control charts that control the same process step, such that the control charts are organized for assignment of the same performance based control limit calculated by using statistics formed by data for control limit values of the control charts.

Abstract translation: 用于同步SPC系统和设备性能控制图的方法和系统具有具有新图表属性的图表模型（22）; 用于计算基于统计偏差的控制限制的方法，用于设置用于检查由SPC系统收集的新数据的时间的同步频率以及用于对控制相同处理步骤的所有控制图进行分类的处理目录，使得控制 组织图表用于分配通过使用由控制图的控制限制值的数据形成的统计计算的相同基于性能的控制限制。

公开(公告)号：US06303510B1

公开(公告)日：2001-10-16

申请号：US09336810

申请日：1999-06-21

Applicant: Wen-Cheng Chien ,  Hui-Chen Chu

Inventor： Wen-Cheng Chien ,  Hui-Chen Chu

IPC: H01L21302

CPC classification number: H01L21/32136

Abstract: A plasma etch method for forming a patterned layer first employs a substrate having formed therover a blanket microelectronic layer. There is also formed over the blanket microelectronic layer a patterned mask layer. There is then etched, while employing a first plasma etch method which employs the patterned mask layer as an etch mask layer, the blanket microelectronic layer to form a partially etched blanket microelectronic layer. There is then etched, while employing a second plasma etch method which employs the patterned mask layer as an etch mask layer, the partially etched blanket microelectronic layer to form a patterned microelectronic layer. Within the present invention, the first plasma etch method employs a higher bias voltage than the second plasma etch method.

Abstract translation: 用于形成图案化层的等离子体蚀刻方法首先采用形成有覆盖的微电子层的衬底。 还在覆盖的微电子层上形成图案化掩模层。 然后蚀刻，同时使用采用图案化掩模层作为蚀刻掩模层的第一等离子体蚀刻方法，覆盖微电子层以形成部分蚀刻的覆盖微电子层。 然后蚀刻，同时使用采用图案化掩模层作为蚀刻掩模层的第二等离子体蚀刻方法，部分蚀刻的覆盖微电子层以形成图案化的微电子层。 在本发明中，第一等离子体蚀刻方法采用比第二等离子体蚀刻方法更高的偏置电压。

公开(公告)号：US6071826A

公开(公告)日：2000-06-06

申请号：US249259

申请日：1999-02-12

Applicant: Ching-Wen Cho ,  Hua-Yu Yang ,  Sen-Fu Chen ,  Chih-Heng Shen ,  Wen-Cheng Chien ,  Chang-Jen Wu ,  Chi-Hsin Lo ,  Hui-Chen Chu

Inventor： Ching-Wen Cho ,  Hua-Yu Yang ,  Sen-Fu Chen ,  Chih-Heng Shen ,  Wen-Cheng Chien ,  Chang-Jen Wu ,  Chi-Hsin Lo ,  Hui-Chen Chu

IPC: H01L21/336 ,  H01L27/146 ,  H01L21/00

CPC classification number: H01L29/6659 ,  H01L27/14601 ,  H01L27/14683

Abstract: A method for forming a CMOS image sensor spacer structure. A polysilicon gate electrode is formed on a substrate; a thin layer of first dielectric is deposited over the exposed surfaces of the gate electrode and the top of the substrate. Next a second layer of dielectric is deposited after which etching is performed to create the electrode spacer. The deposited second layer of dielectric serves as an etch stop and prevents damage to the substrate surface between spacers of the gate electrodes. An alternate method uses a thin ply layer as the stop layer and, in so doing, source/drain damage caused by the white pixel problem.

Abstract translation: 一种用于形成CMOS图像传感器间隔结构的方法。 在基板上形成多晶硅栅电极; 第一电介质的薄层沉积在栅电极和衬底的顶部的暴露表面上。 接下来，沉积第二层电介质，之后进行蚀刻以形成电极间隔物。 沉积的第二介电层用作蚀刻停止层并且防止对栅电极的间隔物之间​​的衬底表面的损坏。 一种替代方法是使用薄层层作为停止层，并且在这样做时，由白色像素问题引起的源/漏损坏。

公开(公告)号：US06624465B1

公开(公告)日：2003-09-23

申请号：US09567417

申请日：2000-05-09

Applicant: Wen-Cheng Chien ,  Hui-Chen Chu

Inventor： Wen-Cheng Chien ,  Hui-Chen Chu

IPC: H01L29788

CPC classification number: H01L29/66825 ,  H01L29/42324

Abstract: A method is provided for forming multi-layer spacer (MLS) for flash EEPROM devices. A composite tetraethyl orthosilicate-silicon nitride (TEOS/Si3N4) layer is deposited over the floating gate and anisotropically etched to form the MLS. The resulting MLS is better controlled dimensionally with the attendant advantage, therefore, of better definition of gate and channel lengths in the memory cell for more predictable and better programming and erase performance of EEPROMs.

Abstract translation: 提供了一种用于形成用于快闪EEPROM器件的多层间隔物（MLS）的方法。 将复合四乙基原硅酸盐 - 氮化硅（TEOS / Si 3 N 4）层沉积在浮动栅极上并进行各向异性蚀刻以形成MLS。 所得到的MLS具有更好的尺寸控制，具有优点，因此，更好地定义存储器单元中的栅极和沟道长度，以更可预测和更好地编程和擦除EEPROM的性能。

公开(公告)号：US06274397B1

公开(公告)日：2001-08-14

申请号：US09323351

申请日：1999-06-01

Applicant: Wen-Cheng Chien ,  Ho-Yin Yiu ,  Hui-Chen Chu

Inventor： Wen-Cheng Chien ,  Ho-Yin Yiu ,  Hui-Chen Chu

IPC: H01L2166

CPC classification number: H01L22/32 ,  G01R31/2896 ,  H01L22/20 ,  H01L2924/014

Abstract: A method for eliminating metal line corrosion for semiconductor packages where exposed metal lines are exposed to the atmosphere for an extended period of time. A passivation layer is deposited over the active die of the semiconductor package, a layer of polymer film is deposited over the passivation layer and over the exposed conducting lines. At the time that the semiconductor package must be tested, including testing for corrosion of the exposed metal lines, the polymer layer is removed and the molding compound is applied. The semiconductor package is now tested. The added step of depositing a layer of polymer film has protected the interconnecting conducting lines from corrosion.

Abstract translation: 一种用于消除暴露的金属线路暴露于大气中延长的时间段的半导体封装的金属线腐蚀的方法。 钝化层沉积在半导体封装的有源裸片上，聚合物膜层沉积在钝化层上并暴露在导电线上。 在半导体封装必须被测试的时候，包括暴露的金属线的腐蚀测试，去除聚合物层并施加模塑料。 该半导体封装已经过测试。 沉积聚合物膜层的添加步骤保护互连导线免受腐蚀。