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    Memory cell device having vertical channel and double gate structure
    1.
    发明授权
    Memory cell device having vertical channel and double gate structure 有权
    具有垂直沟道和双栅结构的存储单元器件

    公开(公告)号：US07863643B2

    公开(公告)日：2011-01-04

    申请号：US12309959

    申请日：2007-09-20

    申请人： Byung Gook Park ,  Il Han Park

    发明人： Byung Gook Park ,  Il Han Park

    IPC分类号： H01L29/66

    CPC分类号： H01L27/115 ,  H01L27/11568

    摘要： A memory cell device having a vertical channel and a double gate structure is provided. More specifically, a memory cell device having a vertical channel and a double gate structure is characterized by having a pillar active region with a predetermined height, which is including a first semiconductor layer forming a first source/drain region, a second semiconductor layer being placed under the first semiconductor layer with a predetermined distance and forming a second source/drain region, and a third semiconductor layer forming a body region and a channel region between the first semiconductor layer and the second semiconductor layer, and therefore, there is no need for unnecessary contacts when it is used as a unit cell for any type of memory array, not to speak of NOR type flash memory array. And the present invention makes to program/erase more effectively and increase the read speed and the amount of sensing current.

    摘要翻译： 提供具有垂直通道和双栅极结构的存储单元器件。 更具体地说，具有垂直沟道和双栅极结构的存储单元器件的特征在于具有预定高度的柱状有源区，其包括形成第一源极/漏极区的第一半导体层，放置第二半导体层的第二半导体层 在第一半导体层之下具有预定距离并形成第二源极/漏极区域，以及形成第一半导体层和第二半导体层之间的体区域和沟道区域的第三半导体层，因此不需要 当它被用作任何类型的存储器阵列的单位单元时，不用说NOR型闪存阵列就是不必要的接触。 并且本发明使得更有效地编程/擦除并增加读取速度和感测电流的量。

    NONVOLATILE MEMORY DEVICE HAVING NEAR/FAR MEMORY CELL GROUPINGS AND DATA PROCESSING METHOD
    2.
    发明申请
    NONVOLATILE MEMORY DEVICE HAVING NEAR/FAR MEMORY CELL GROUPINGS AND DATA PROCESSING METHOD 审中-公开
    具有近似/无效存储单元分组和数据处理方法的非易失性存储器件

    公开(公告)号：US20140056069A1

    公开(公告)日：2014-02-27

    申请号：US13935596

    申请日：2013-07-05

    申请人： IL HAN PARK ,  SEUNG-BUM KIM ,  GOEUN JUNG

    发明人： IL HAN PARK ,  SEUNG-BUM KIM ,  GOEUN JUNG

    IPC分类号： G11C16/04 ,  G11C16/24

    CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3459

    摘要： A nonvolatile memory device includes; a memory cell array designating a first memory cell group including first memory cells connected with a word line and disposed less than a reference distance from a word line voltage source in a word line direction, and a second memory cell group including second memory cells connected to the word line and disposed more than the reference distance from the word line voltage source in the word line direction, and control logic configured during a data processing operation to provide a first word line voltage to a first target memory cell among the first memory cells, and a second word line voltage different from the first word line voltage to a second target memory cell among the second memory cells.

    摘要翻译： 非易失性存储装置包括： 存储单元阵列，其指定第一存储单元组，所述第一存储单元组包括与字线连接并且设置为小于字线电压源在字线方向上的参考距离的第一存储单元;以及第二存储单元组，包括连接到 所述字线并且设置在所述字线方向上比所述字线电压源的参考距离大，以及在数据处理操作期间配置的控制逻辑，以向所述第一存储器单元中的第一目标存储单元提供第一字线电压， 以及与第一字线电压不同的第二字线电压到第二存储单元中的第二目标存储单元。

    NAND type flash memory array and method for operating the same
    4.
    发明授权
    NAND type flash memory array and method for operating the same 有权
    NAND型闪存阵列及其操作方法

    公开(公告)号：US07502262B2

    公开(公告)日：2009-03-10

    申请号：US11423691

    申请日：2006-06-12

    申请人： Byung-Gook Park ,  Tae-Hoon Kim ,  Il-Han Park

    发明人： Byung-Gook Park ,  Tae-Hoon Kim ,  Il-Han Park

    IPC分类号： G11C16/04 ,  G11C16/12

    CPC分类号： G11C16/0483 ,  H01L27/115

    摘要： A NAND type flash memory array which is composed of a plurality of memory cells with a shallow junction on an SOI substrate to make the body region depleted fully when each channel of the memory cells is turned on is provided. The invention improves the efficiency of a reading operation, enables an erasing operation on the SOI structure and enables use of a low voltage VPASS instead of a high voltage VPASS, which is used for a programming operation in a conventional NAND type flash memory array, and therefore it diminishes programming disturbance more effectively than a conventional array.

    摘要翻译： 提供一种NAND型闪速存储器阵列，其由在SOI衬底上具有浅结的多个存储单元组成，以在存储器单元的每个通道被接通时使身体区域完全耗尽。 本发明提高了读取操作的效率，能够对SOI结构进行擦除操作，并且能够使用用于常规NAND型闪存阵列中的编程操作的低电压VPASS代替高电压VPASS，以及 因此它比常规阵列更有效地减少编程干扰。

    Fusing device for image forming apparatus
    5.
    发明申请
    Fusing device for image forming apparatus 失效
    图像形成装置用定影装置

    公开(公告)号：US20050063744A1

    公开(公告)日：2005-03-24

    申请号：US10943148

    申请日：2004-09-17

    申请人： In-gu Kwak ,  Il-han Park

    发明人： In-gu Kwak ,  Il-han Park

    IPC分类号： G03G15/20

    CPC分类号： G03G15/2053

    摘要： A fusing device for an image forming apparatus including a cylindrical fusing roller, a pressure roller installed opposite to the fusing roller and pressing a sheet of paper passing therebetween, and an inductive heating element simultaneously heating the fusing roller and the pressure roller. The fusing device reduces the time to reach a fusing temperature by heating both the fusing roller and the pressure roller with a closed magnetic core extending between hollow portions of each.

    摘要翻译： 一种用于图像形成装置的定影装置，包括圆柱形定影辊，与定影辊相对安装的压力辊，并且压过通过它们的纸张之间的图像形成装置，以及感应加热元件，同时加热定影辊和加压辊。 定影装置通过利用在每个的中空部分之间延伸的封闭的磁芯加热定影辊和加压辊来缩短达到定影温度的时间。

    NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY SYSTEM, PROGRAM METHOD THEREOF, AND OPERATION METHOD OF CONTROLLER CONTROLLING THE SAME
    7.
    发明申请
    NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY SYSTEM, PROGRAM METHOD THEREOF, AND OPERATION METHOD OF CONTROLLER CONTROLLING THE SAME 有权
    非易失性存储器件，非易失性存储器系统，其程序方法及其控制器的操作方法

    公开(公告)号：US20130188426A1

    公开(公告)日：2013-07-25

    申请号：US13618605

    申请日：2012-09-14

    申请人： Il Han PARK ,  Yongsung CHO ,  Sang-Soo PARK

    发明人： Il Han PARK ,  Yongsung CHO ,  Sang-Soo PARK

    IPC分类号： G11C16/10

    CPC分类号： G11C16/10 ,  G11C16/24 ,  G11C16/3427

    摘要： According to example embodiments, a nonvolatile memory device includes a first memory cell configured to store a first data pattern, a second memory cell configured to be programmed using a program voltage, and a coupling program control unit. The coupling program control unit may be configured to perform a verification operation for verifying whether the first memory cell is programmed with the first data pattern. The verification operation may provide to the first memory cell a verification voltage corresponding to the first data pattern. The coupling program control unit may be configured to end programming the second memory cell when the verification operation on the first memory cell indicates a pass.

    摘要翻译： 根据示例性实施例，非易失性存储器件包括被配置为存储第一数据模式的第一存储器单元，被配置为使用编程电压进行编程的第二存储器单元和耦合程序控制单元。 耦合程序控制单元可以被配置为执行用于验证第一存储单元是否用第一数据模式编程的验证操作。 验证操作可以向第一存储器单元提供对应于第一数据模式的验证电压。 耦合程序控制单元可以被配置为当对第一存储器单元的验证操作指示通过时，结束对第二存储器单元的编程。

    Nonvolatile memory device and method of fabricating the same
    8.
    发明申请
    Nonvolatile memory device and method of fabricating the same 审中-公开
    非易失性存储器件及其制造方法

    公开(公告)号：US20080087940A1

    公开(公告)日：2008-04-17

    申请号：US11589994

    申请日：2006-10-31

    申请人： Soo-doo Chae ,  Chung-woo Kim ,  Chan-jin Park ,  Jeong-hee Han ,  Byung-gook Park ,  Il-han Park

    发明人： Soo-doo Chae ,  Chung-woo Kim ,  Chan-jin Park ,  Jeong-hee Han ,  Byung-gook Park ,  Il-han Park

    IPC分类号： H01L29/792 ,  H01L21/8238

    CPC分类号： H01L29/792 ,  H01L29/66833 ,  H01L29/7926

    摘要： A nonvolatile memory device, includes a semiconductor substrate having a bottom part, a second vertical part positioned vertically on the bottom part, and a first vertical part having a width smaller than a width of the second vertical part and positioned on the second vertical part to have a boundary step therebetween; a charge trap layer disposed on a lateral surface of the first vertical part and on an upper surface of the boundary step; and a control gate electrode disposed on an upper surface of the bottom part and on lateral surfaces of the second vertical part and the charge trap layer.

    摘要翻译： 一种非易失性存储器件，包括：半导体衬底，具有底部;垂直于第二垂直方向的底部;以及第一垂直部分，其宽度小于第二垂直部分的宽度，并且位于第二垂直部分上， 在其间具有边界步骤; 电荷陷阱层，设置在所述第一垂直部分的侧表面和所述边界台阶的上表面上; 以及设置在所述底部的上表面和所述第二垂直部分和所述电荷陷阱层的侧表面上的控制栅电极。

    Fusing device of an image forming apparatus and method thereof
    9.
    发明授权
    Fusing device of an image forming apparatus and method thereof 有权
    图像形成装置的定影装置及其方法

    公开(公告)号：US07158748B2

    公开(公告)日：2007-01-02

    申请号：US10960093

    申请日：2004-10-08

    申请人： In-gu Kwak ,  Il-han Park

    发明人： In-gu Kwak ,  Il-han Park

    IPC分类号： G03G15/20

    CPC分类号： G03G15/2053 ,  G03G2215/2016 ,  G03G2215/2035

    摘要： A fusing device of an image forming apparatus and method thereof are provided. The fusing device and method include a conductive member having a linear portion for contacting a printing medium, a fusing film for sliding on a circumference of the conductive member, a pressing roller for contacting the fusing film in the linear portion, forming a fusing nip area, and rotating the fusing film, and an induction heating unit for heating the conductive member by induction and generating heat. The thickness of the conductive member in the fusing nip area is smaller than the thickness of the conductive member in other areas.

    摘要翻译： 提供了图像形成装置的定影装置及其方法。 定影装置和方法包括具有用于接触打印介质的线性部分的导电构件，用于在导电构件的圆周上滑动的定影膜，用于使直线部分中的定影膜接触的加压辊，形成定影夹持区域 并且使定影膜旋转，以及感应加热单元，用于通过感应加热导电构件并产生热量。 定影夹持区域中的导电构件的厚度小于其它区域中的导电构件的厚度。