公开(公告)号：US09425772B2

公开(公告)日：2016-08-23

申请号：US13528725

申请日：2012-06-20

申请人： Wojciech Jakub Poppe ,  Ilyas Elkin ,  Puneet Gupta

发明人： Wojciech Jakub Poppe ,  Ilyas Elkin ,  Puneet Gupta

IPC分类号： H03K3/03 ,  G01R31/28

CPC分类号： H03K3/0315 ,  G01R31/2853

摘要： The described systems and methods can facilitate examination of device parameters including analysis of relatively dominant characteristic impacts on delays. In one embodiment, at least some coupling components (e.g., metal layer wires, traces, lines, etc.) have a relatively dominant impact on delays and the delay is in part a function of both capacitance and resistance of the coupling component. In one embodiment, a system comprises a plurality of dominant characteristic oscillating rings, wherein each respective one of the plurality of dominant characteristic oscillating rings includes a respective dominant characteristic. Additional analysis can be performed correlating the dominant characteristic delay impact results with device fabrication and operation.

摘要翻译： 所描述的系统和方法可以便于检查设备参数，包括对延迟的相对主导的特征影响的分析。 在一个实施例中，至少一些耦合部件（例如，金属层导线，迹线，线等）对延迟具有相对主要的影响，延迟部分地是耦合部件的电容和电阻的函数。 在一个实施例中，系统包括多个主要特征振荡环，其中多个主要特性振荡环中的每个相应的一个包括相应的主要特性。 可以进行附加分析，将主要特征延迟影响结果与器件制造和操作相关联。

公开(公告)号：US20130021107A1

公开(公告)日：2013-01-24

申请号：US13556129

申请日：2012-07-23

申请人： Wojciech Jakub Poppe ,  Puneet Gupta ,  Ilyas Elkin

发明人： Wojciech Jakub Poppe ,  Puneet Gupta ,  Ilyas Elkin

IPC分类号： H03K3/03

CPC分类号： H03K3/0315 ,  G01R31/2831 ,  G01R31/31725 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Component characteristics analysis systems and methods are described. In one embodiment, a ring oscillator comprises: at least one inversion stage operable to cause a signal transition; a target component that has an increased comparative impact or influence on a signal transition propagation in the ring oscillator; and an output component for outputting an indication of the impact the target component has on the signal transition. The target component can include a plurality of vias from one metal layer to another metal layer. The plurality of vias from one metal layer to another metal layer can be configured in a cell. The vias can correspond to a via layer. In one exemplary implementation, the output is coupled to an analysis component. The analysis component can include correlation of the via resistance into a wafer variations and generate a wafer map. The analysis component can include correlation of the via resistance into a wafer.

摘要翻译： 描述了组件特性分析系统和方法。 在一个实施例中，环形振荡器包括：可操作以引起信号转换的至少一个反转级; 具有对环形振荡器中的信号跃迁传播的增加的比较影响或影响的目标分量; 以及输出部件，用于输出目标部件对信号转换的影响的指示。 目标部件可以包括从一个金属层到另一个金属层的多个通孔。 从一个金属层到另一个金属层的多个通孔可以配置在电池中。 过孔可以对应于通孔层。 在一个示例性实现中，输出耦合到分析组件。 分析组件可以包括通孔电阻与晶片变化的相关性并产生晶片图。 分析组件可以包括通孔电阻与晶片的相关性。

公开(公告)号：US09496853B2

公开(公告)日：2016-11-15

申请号：US13556129

申请日：2012-07-23

申请人： Wojciech Jakub Poppe ,  Puneet Gupta ,  Ilyas Elkin

发明人： Wojciech Jakub Poppe ,  Puneet Gupta ,  Ilyas Elkin

IPC分类号： H03K3/03 ,  G01R31/317 ,  H01L21/66 ,  G01R31/28

CPC分类号： H03K3/0315 ,  G01R31/2831 ,  G01R31/31725 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Component characteristics analysis systems and methods are described. In one embodiment, a ring oscillator comprises: at least one inversion stage operable to cause a signal transition; a target component that has an increased comparative impact or influence on a signal transition propagation in the ring oscillator; and an output component for outputting an indication of the impact the target component has on the signal transition. The target component can include a plurality of vias from one metal layer to another metal layer, which can be configured in a cell. The vias can correspond to a via layer. In one exemplary implementation, the output is coupled to an analysis component. The analysis component can include correlation of the via resistance into a wafer variations and generate a wafer map and can include correlation of the via resistance into a wafer.

摘要翻译： 描述了组件特性分析系统和方法。 在一个实施例中，环形振荡器包括：可操作以引起信号转换的至少一个反转级; 具有对环形振荡器中的信号跃迁传播的增加的比较影响或影响的目标分量; 以及输出部件，用于输出目标部件对信号转换的影响的指示。 目标部件可以包括从一个金属层到另一个金属层的多个通孔，其可以配置在电池中。 过孔可以对应于通孔层。 在一个示例性实现中，输出耦合到分析组件。 分析组件可以包括通孔电阻与晶片变化的相关性并产生晶片图，并且可以包括通孔电阻与晶片的相关性。

公开(公告)号：US20130027140A1

公开(公告)日：2013-01-31

申请号：US13528725

申请日：2012-06-20

申请人： Wojciech Jakub Poppe ,  Ilyas Elkin ,  Puneet Gupta

发明人： Wojciech Jakub Poppe ,  Ilyas Elkin ,  Puneet Gupta

IPC分类号： G01R27/04 ,  H03K3/03

CPC分类号： H03K3/0315 ,  G01R31/2853

摘要： The described systems and methods can facilitate examination of device parameters including analysis of relatively dominant characteristic impacts on delays. In one embodiment, at least some coupling components (e.g., metal layer wires, traces, lines, etc.) have a relatively dominate impact on delays and the delay is in part a function of both capacitance and resistance of the coupling component. In one embodiment, a system comprises a plurality of dominate characteristic oscillating rings, wherein each respective one of the plurality of dominate characteristic oscillating rings includes a respective dominate characteristic. Additional analysis can be performed correlating the dominate characteristic delay impact results with device fabrication and operation.

摘要翻译： 所描述的系统和方法可以便于检查设备参数，包括对延迟的相对主导的特征影响的分析。 在一个实施例中，至少一些耦合部件（例如，金属层导线，迹线，线等）对延迟具有相对主导的影响，延迟部分地是耦合部件的电容和电阻的函数。 在一个实施例中，系统包括多个主要的特征振荡环，其中多个主要特征振荡环中的每一个包括相应的主导特性。 可以进行附加分析，将主导特征延迟影响结果与设备制造和操作相关联。

公开(公告)号：US09210538B2

公开(公告)日：2015-12-08

申请号：US13425849

申请日：2012-03-21

申请人： Puneet Gupta ,  Akshay Darbari ,  Venkat Kumar Sivaramamurthy

发明人： Puneet Gupta ,  Akshay Darbari ,  Venkat Kumar Sivaramamurthy

IPC分类号： H04W24/00 ,  H04W4/02 ,  H04W4/00 ,  H04W64/00

CPC分类号： H04W4/02 ,  H04W4/50 ,  H04W64/00

摘要： The present invention relates to a computer-implemented method, system and computer readable medium for providing context-based listing services. The method comprises registering at least one first service provider with an second service provider wherein registering comprises that the first service provider provides the information via a communication network to the second service provider and it validates the information. Validating comprises identify the location of the first service provider and/or request to at least one predefined user located nearby the location of the first service provider. At least one user requests the second service provider for the information via the communication network. At least one user retrieves the information and provides ranking to category of services so as to update the information in the second service provider.

摘要翻译： 本发明涉及一种用于提供基于上下文的列表服务的计算机实现的方法，系统和计算机可读介质。 该方法包括向第二服务提供商注册至少一个第一服务提供商，其中注册包括第一服务提供商经由通信网络向第二服务提供商提供信息，并验证该信息。 验证包括将位于第一服务提供商的位置附近的至少一个预定义用户识别第一服务提供商的位置和/或请求。 至少一个用户通过通信网络请求第二服务提供商的信息。 至少一个用户检索信息并提供对服务类别的排名，以便更新第二服务提供商中的信息。

公开(公告)号：US09064538B2

公开(公告)日：2015-06-23

申请号：US13311795

申请日：2011-12-06

申请人： Puneet Gupta ,  Akshay Darbari ,  Karthik Gopalakrishnan Vinmani ,  Venkat Kumar Sivaramamurthy

发明人： Puneet Gupta ,  Akshay Darbari ,  Karthik Gopalakrishnan Vinmani ,  Venkat Kumar Sivaramamurthy

IPC分类号： H04N5/93 ,  G11B27/034 ,  G11B27/10 ,  G11B27/28 ,  G11B27/34

CPC分类号： G11B27/034 ,  G11B27/105 ,  G11B27/28 ,  G11B27/34

摘要： A method, a system, and a computer program product code for generating a series of still images from an input video file are provided. The series of still images may include, but are not limited to, a comic strip and a storyboard. The method includes extracting audio and visual frames from the video file. Thereafter, basic units of the video file are identified. The basic units are exposition (beginning), conflict (middle), and resolution (end). Thereafter, key frames are extracted from the basic units based on at least one of audio frames, visual frames, and a combination of the visual frames and the audio frames. Then, the extracted key frames are manipulated to output a series of still images. Subsequently, narration in the form of audio or text is attached to the still images to generate at least one of comic strips and storyboards.

摘要翻译： 提供了一种用于从输入视频文件生成一系列静止图像的方法，系统和计算机程序产品代码。 一系列静止图像可以包括但不限于漫画和故事板。 该方法包括从视频文件中提取音视频帧。 此后，识别视频文件的基本单元。 基本单位是博览会（开始），冲突（中间）和分辨率（结束）。 此后，基于音频帧，视觉帧以及视觉帧和音频帧的组合中的至少一个，从基本单元提取关键帧。 然后，操作所提取的关键帧以输出一系列静止图像。 随后，将音频或文本形式的叙述附加到静止图像以产生漫画和故事板中的至少一个。

公开(公告)号：US08956584B2

公开(公告)日：2015-02-17

申请号：US13328029

申请日：2011-12-16

申请人： Puneet Gupta ,  Yue Huang ,  Satish Bhusarapu

发明人： Puneet Gupta ,  Yue Huang ,  Satish Bhusarapu

IPC分类号： C01B33/03 ,  B01J8/24 ,  C01B33/04

CPC分类号： C01B33/027 ,  C01B33/03

摘要： Production of polycrystalline silicon in substantially closed-loop processes and systems is disclosed. The processes and systems generally involve disproportionation of trichlorosilane to produce silane or dichlorosilane and thermal decomposition of silane or dichlorosilane to produce polycrystalline silicon.

摘要翻译： 公开了在基本闭环过程和系统中生产多晶硅。 方法和系统通常涉及三氯硅烷的歧化以产生硅烷或二氯硅烷以及硅烷或二氯硅烷的热分解以产生多晶硅。

公开(公告)号：US08949768B2

公开(公告)日：2015-02-03

申请号：US13620669

申请日：2012-09-14

申请人： Puneet Gupta ,  Andrew B. Kahng

发明人： Puneet Gupta ,  Andrew B. Kahng

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5081 ,  G06F17/5063 ,  G06F17/5068 ,  G06F2217/78

摘要： A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

摘要翻译： 公开了一种标准细胞库。 标准单元库包含其中注释至少一个单元中的至少一个晶体管用于栅长度偏置的单元。 栅极长度偏置包括栅极长度的修改，以便改变修改的栅极长度的速度或功率消耗。 标准单元库是用于制造半导体器件（例如，作为半导体芯片的结果）的方法，通过制造在几何形状的一个或多个布局上限定的特征。 注释用于在使用用于制造半导体器件的几何形状之前识别哪些晶体管栅极特征将被修改。

公开(公告)号：US08524048B2

公开(公告)日：2013-09-03

申请号：US12898494

申请日：2010-10-05

申请人： Zhihui Gu ,  Timothy D. Truong ,  Puneet Gupta

发明人： Zhihui Gu ,  Timothy D. Truong ,  Puneet Gupta

IPC分类号： B01D3/14 ,  C01B33/04 ,  F25J1/00

CPC分类号： B01D3/143

摘要： Processes and systems for purifying silane-containing streams are disclosed with relatively less silane being lost in impurity streams by use of distillation and/or condensation operations.

摘要翻译： 公开了用于纯化含硅烷料流的方法和系统，通过使用蒸馏和/或冷凝操作，相对较少的硅烷在杂质流中损失。

公开(公告)号：US08490043B2

公开(公告)日：2013-07-16

申请号：US12717887

申请日：2010-03-04

申请人： Puneet Gupta ,  Andrew B. Kahng

发明人： Puneet Gupta ,  Andrew B. Kahng

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5063 ,  G06F17/5068 ,  G06F2217/78

摘要： A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.