公开(公告)号：US06601197B1

公开(公告)日：2003-07-29

申请号：US09456259

申请日：1999-12-07

Applicant: Isao Naritake

Inventor： Isao Naritake

IPC: G11C2900

CPC classification number: G11C29/48 ,  G11C11/401 ,  G11C2207/104

Abstract: A semiconductor memory device is provided with an MPU, a secondary cache and a TAG memory mounted on a chip. Registers are provided for a plurality of test data buses connected parallel to a plurality of data buses from the MPU to the secondary cache or the TAG memory. The registers and the plurality of data buses of the MPU are changed with switches so as to be connected with a bonding pad which is a part of an external terminal for the MPU. With this arrangement, the semiconductor memory device can connect with a tester for a DRAM part test via the bonding pad.

Abstract translation: 半导体存储器件设置有MPU，二级缓存和安装在芯片上的TAG存储器。 寄存器被提供用于并行连接到从MPU到二级高速缓存或TAG存储器的多条数据总线的多个测试数据总线。 MPU的寄存器和多个数据总线用开关改变，以便与作为MPU的外部端子的一部分的接合焊盘连接。 通过这种布置，半导体存储器件可以通过焊盘与用于DRAM部件测试的测试器连接。

公开(公告)号：US6038184A

公开(公告)日：2000-03-14

申请号：US65280

申请日：1998-04-23

Applicant: Isao Naritake

Inventor： Isao Naritake

IPC: G11C11/407 ,  G11C7/00 ,  G11C7/10 ,  G11C7/18 ,  G11C7/22 ,  G11C11/401

CPC classification number: G11C7/1018 ,  G11C7/1021 ,  G11C7/18 ,  G11C7/22

Abstract: A semiconductor dynamic random access memory device serially reads out data bits from and serially writes data bits into memory cells through a long burst cycle, and the data bits are transferred between a read/write data bus to data latch circuits, between the data latch circuits and the main/sub sense amplifiers and the main/sub sense amplifiers and the sub-bit line pairs; while the data bits are being stepwise transferred between the memory cells and the read/write data bus, an internal timing controller not only provides activation timings and deactivation timings to the main-sub sense amplifiers and transfer gate arrays but also the starting point and the end point of the long burst cycle so that the semiconductor dynamic random access memory device is fabricated on a relatively small semiconductor chip.

Abstract translation: 半导体动态随机存取存储器件通过长突发周期串行读出数据位并将数据位串行地写入存储单元，数据位在数据锁存电路之间的数据锁存电路之间传输到读/写数据总线 主/副感测放大器和主/副读出放大器和子位线对; 而数据位在存储器单元和读/写数据总线之间逐步传送时，内部定时控制器不仅向主子读出放大器和传输门阵列提供激活定时和去激活定时，而且还提供起始点和 长突发周期的终点，使得半导体动态随机存取存储器件制造在相对较小的半导体芯片上。

公开(公告)号：US5406526A

公开(公告)日：1995-04-11

申请号：US129363

申请日：1993-09-30

Applicant: Tadahiko Sugibayashi ,  Mamoru Fujita ,  Isao Naritake

Inventor： Tadahiko Sugibayashi ,  Mamoru Fujita ,  Isao Naritake

IPC: G11C11/408 ,  G11C11/4091 ,  G11C8/00

CPC classification number: G11C11/408 ,  G11C11/4091

Abstract: A dynamic random access memory device selects a row of memory cells from a plurality of memory cell sub-arrays with main word lines and sub-word lines for a data access, and data bits read out from the row of memory cells are amplified by a sense amplifier circuit array, wherein a row block address decoder and a column block address decoder supply a first enable signal and a second enable signal to a row of memory cell sub-arrays and a column of memory cell sub-arrays so that only one of the sense amplifier circuit arrays is powered for the amplification, thereby decreasing peak current consumed by the sense amplifier circuit arrays.

Abstract translation: 动态随机存取存储器装置从具有用于数据存取的主字线和子字线的多个存储单元子阵列中选择一行存储单元，从存储单元行读出的数据位由 读出放大器电路阵列，其中行块地址解码器和列块地址解码器向一行存储器单元子阵列和一列存储器单元子阵列提供第一使能信号和第二使能信号，使得仅一个 感测放大器电路阵列被供电用于放大，从而减少由读出放大器电路阵列消耗的峰值电流。

公开(公告)号：US08432717B2

公开(公告)日：2013-04-30

申请号：US12898210

申请日：2010-10-05

Applicant: Hiroyuki Furukawa ,  Isao Naritake

Inventor： Hiroyuki Furukawa ,  Isao Naritake

IPC: G11C17/12

CPC classification number: G11C17/165 ,  G11C17/12 ,  G11C17/18

Abstract: Provided is a semiconductor integrated circuit including: an anti-fuse element that electrically connects a first node and a first power supply terminal when data is written and electrically disconnect the first node and the first power supply terminal when data is not written; a first switch circuit that is connected between the first node and a first data line applied with a predetermine first voltage, and enters an off state from an on state according to a first control signal; and a detection part that detects write data of the anti-fuse element according to whether a voltage of the first node is substantially the same as the first voltage or substantially the same as a supply voltage of the first power supply terminal when the first switch circuit enters the off state.

Abstract translation: 提供一种半导体集成电路，包括：当数据被写入时电连接第一节点和第一电源端子的反熔丝元件，当数据未被写入时电熔断第一节点和第一电源端子; 第一开关电路，连接在第一节点和施加预定第一电压的第一数据线之间，并根据第一控制信号从接通状态进入截止状态; 以及检测部，其根据所述第一节点的电压与所述第一电压基本相同还是与所述第一电源端子的电源电压基本相同时，检测所述反熔丝元件的写入数据，所述第一开关电路 进入关闭状态。

公开(公告)号：US20070236277A1

公开(公告)日：2007-10-11

申请号：US11783432

申请日：2007-04-09

Applicant: Isao Naritake

Inventor： Isao Naritake

IPC: H03K3/01

CPC classification number: H03K5/135 ,  G05F3/205 ,  H03K5/133 ,  H03K5/26 ,  H03K2005/00032 ,  H03K2005/00104

Abstract: A semiconductor integrated circuit device includes: a first bias generating circuit, a second bias generating circuit and a control circuit. The first bias generating circuit generates a first substrate bias voltage of a P-channel transistor. The second bias generating circuit generates a second substrate bias voltage of N-channel transistor. The control circuit controls the first bias generating circuit and the second bias generating circuit independently on the basis of operating states of circuits to which the first substrate bias voltage and the second substrate bias voltage are applied.

Abstract translation: 一种半导体集成电路器件，包括：第一偏置产生电路，第二偏置产生电路和控制电路。 第一偏置产生电路产生P沟道晶体管的第一衬底偏置电压。 第二偏置产生电路产生N沟道晶体管的第二衬底偏置电压。 控制电路基于施加了第一衬底偏置电压和第二衬底偏置电压的电路的操作状态独立地控制第一偏置产生电路和第二偏置产生电路。

公开(公告)号：US06577543B2

公开(公告)日：2003-06-10

申请号：US09902842

申请日：2001-07-11

Applicant: Isao Naritake

Inventor： Isao Naritake

IPC: G11C700

CPC classification number: G11C29/12 ,  G11C11/4074 ,  G11C2207/104

Abstract: A semiconductor integrated circuit, includes a first macro and a second macro. The first macro outputs a data signal. The second macro inputs the data signal. The first macro fixes the data signal at a non-high level state that is not a high level in response to a control signal.

公开(公告)号：US6130845A

公开(公告)日：2000-10-10

申请号：US161954

申请日：1998-09-29

Applicant: Tetsuya Ootsuki ,  Isao Naritake

Inventor： Tetsuya Ootsuki ,  Isao Naritake

IPC: G11C11/401 ,  G11C7/06 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C11/56 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC classification number: G11C11/4097 ,  G11C11/4091 ,  G11C11/565 ,  G11C7/06 ,  G11C7/18 ,  G11C16/24

Abstract: There is provided a dynamic type semiconductor memory device including (a) a first hierarchized complementary bit line, (b) a second hierarchized complementary bit line, (c) a first sense-amplifier electrically connected to the first bit line, (d) at least one second sense-amplifier electrically connected to both the first bit line and the second bit line, (e) a capacitor located between the first and second bit lines for each of second sense-amplifiers, and (f) a transfer gate arranged in series with the capacity between the first and second bit lines. The above-mentioned dynamic type semiconductor memory device makes it possible to store two-bit data in a single memory cell by employing a memory cell comprised of one transistor and one capacitor, without the use of a conventional memory cell having two transistors and one capacitor. Hence, the dynamic type semiconductor memory device ensures a significant reduction in a chip area.

Abstract translation: 提供了一种动态型半导体存储器件，它包括：（a）第一级互补位线，（b）第二级互补位线，（c）与第一位线电连接的第一读出放大器，（d） 电连接到第一位线和第二位线的至少一个第二读出放大器，（e）位于第二和第二位线之间的用于每个第二读出放大器的电容器，以及（f）布置在 系列具有第一和第二位线之间的容量。 上述动态型半导体存储器件可以通过采用由一个晶体管和一个电容器组成的存储单元而将两位数据存储在单个存储单元中，而不需要使用具有两个晶体管和一个电容器的传统存储单元 。 因此，动态型半导体存储器件确保芯片面积的显着减少。

公开(公告)号：US5631872A

公开(公告)日：1997-05-20

申请号：US658210

申请日：1996-06-04

Applicant: Isao Naritake ,  Tadahiko Sugibayashi ,  Satoshi Utsugi ,  Tatsunori Murotani

Inventor： Isao Naritake ,  Tadahiko Sugibayashi ,  Satoshi Utsugi ,  Tatsunori Murotani

IPC: G11C11/401 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4094 ,  G11C7/00

CPC classification number: G11C11/4074 ,  G11C11/406 ,  G11C11/4094

Abstract: A data refresh is indispensable for a semiconductor dynamic random access memory device, and electric charges are recycled from bit line pairs for a row of memory cell arrays to power supply lines for bit line drivers associated with the next row of memory cell arrays and from bit line pairs for the next row of memory cell arrays to power supply lines for the row of memory cell arrays, thereby reducing power consumption in the data refresh.

Abstract translation: 数据刷新对于半导体动态随机存取存储器件是不可缺少的，并且电荷从一行存储单元阵列的位线对再循环到与下一行存储单元阵列相关联的位线驱动器的电源线 用于下一行存储单元阵列的线对，用于为行存储单元阵列供电线，从而降低数据刷新中的功耗。

公开(公告)号：US06208563B1

公开(公告)日：2001-03-27

申请号：US09468294

申请日：1999-12-21

Applicant: Isao Naritake

Inventor： Isao Naritake

IPC: G11C700

CPC classification number: G11C7/1018 ,  G11C11/4096

Abstract: A semiconductor memory device such as a DRAM device in which, in each write or read cycle, a plurality bits of data are written to or read from memory cells as a burst. The semiconductor memory device includes: a plurality of write/read circuits for reading data from selected memory cells to data lines and writing data from the data lines to selected memory cells; a column selector for distributing data from an input/output line to the data lines, and outputting data from the data lines to the input/output line; and a plurality of data latches inserted into data line circuit portions between the column selector and the write/read circuits, for temporarily storing data to be written to or read from the memory cells as a burst. In a write cycle, after data stored in the latches is written into memory cells and after elapsing a predetermined time period required for a precharge operation of the bit lines, the next write cycle is started. In a read cycle, after data is read out from memory cells into the data latches and after performing a precharge operation of the bit lines, the next read cycle is started.

Abstract translation: 诸如DRAM器件的半导体存储器件，其中在每个写入或读取周期中将多个数据位作为突发写入存储器单元或从存储器单元读取。 半导体存储器件包括：多个读/写电路，用于将数据从选定的存储单元读取到数据线，并将数据从数据线写入选择的存储单元; 用于将数据从输入/输出线分配到数据线的列选择器，并将数据从数据线输出到输入/输出线; 以及插入列选择器和写/读电路之间的数据线电路部分中的多个数据锁存器，用于临时存储要作为突发写入或从存储器单元读取的数据。 在写入周期中，将存储在锁存器中的数据写入存储单元之后，并且在经过位线的预充电操作所需的预定时间段之后，开始下一个写入周期。 在读周期中，在将数据从存储器单元读出到数据锁存器中之后并且在执行位线的预充电操作之后，开始下一个读取周期。

公开(公告)号：US6151237A

公开(公告)日：2000-11-21

申请号：US292665

申请日：1999-04-16

Applicant: Isao Naritake

Inventor： Isao Naritake

IPC: G11C7/10 ,  G11C7/18 ,  G11C11/4097 ,  G11C11/56 ,  G11C5/06

CPC classification number: G11C11/565 ,  G11C11/4097 ,  G11C7/1006 ,  G11C7/18 ,  G11C16/24

Abstract: In a dynamic type semiconductor memory device having a classified bit line structure, a feedback capacitor is provided between sub-bit lines and main bit lines of a sub-sense amplifier. A voltage difference read out on the sub-bit lines is transferred to the main bit lines, the read out voltage difference is amplified by a main sense amplifier, and data of superordinate bits is read out. At the same time, the data on said main bit lines is feed-backed to the sub-bit lines through the capacitor. Thereafter, a reading operation from the sub-bit lines to the main bit lines is performed again, thereby enabling a reading operation for data of subordinate bits. Thus, in a dynamic type semiconductor memory device having a conventional memory cell structure, data for two bits can be stored in one memory cell.

Abstract translation: 在具有分类的位线结构的动态型半导体存储器件中，在子读出放大器的子位线和主位线之间提供反馈电容器。 在子位线上读出的电压差被传送到主位线，读出的电压差被主读出放大器放大，并且读出上位的数据。 同时，所述主位线上的数据通过电容器馈送到子位线。 此后，再次执行从子位线到主位线的读取操作，从而能够进行从属位数据的读取操作。 因此，在具有传统的存储单元结构的动态类型的半导体存储器件中，可将两位的数据存储在一个存储单元中。