公开(公告)号：US09110486B2

公开(公告)日：2015-08-18

申请号：US13605662

申请日：2012-09-06

申请人： Joshua Siegel ,  Khoi B. Mai

发明人： Joshua Siegel ,  Khoi B. Mai

IPC分类号： G05F3/30

CPC分类号： G05F3/30

摘要： A band gap reference circuit including a band gap reference generator having an output for providing a reference voltage and a startup circuit for controlling current provided to the band gap reference generator when activated. The startup circuit includes a turnoff circuit having an output to deactivate the startup circuit to not control current to the band gap reference generator based on a voltage of the output of the band gap reference generator. The turnoff circuit includes an inverter having a first transistor of a first conductivity type in series with a second transistor of a second conductivity type opposite the first conductivity type. The startup circuit includes a body bias circuit connected to a body of the first transistor to provide a voltage differential between the body of the first transistor and a source terminal of the first transistor.

摘要翻译： 一种带隙参考电路，包括具有用于提供参考电压的输出的带隙基准发生器和用于当被激活时控制提供给带隙基准发生器的电流的启动电路。 启动电路包括具有输出的开关电路，该输出用于基于带隙基准发生器的输出的电压来停止启动电路以不控制到带隙基准发生器的电流。 所述截止电路包括具有与第一导电类型相反的第二导电类型的第二晶体管串联的第一导电类型的第一晶体管的反相器。 启动电路包括连接到第一晶体管的主体的主体偏置电路，以在第一晶体管的主体和第一晶体管的源极之间提供电压差。

公开(公告)号：US07898323B2

公开(公告)日：2011-03-01

申请号：US12479140

申请日：2009-06-05

申请人： Joshua Siegel ,  Hector Sanchez

发明人： Joshua Siegel ,  Hector Sanchez

IPC分类号： H03F1/02

CPC分类号： H03F3/45968 ,  H03F2203/45048

摘要： An amplifying circuit has an offset calibration mode and a normal mode. The amplifying circuit includes an amplifier having a non-inverting input and an inverting input for receiving, during the normal mode, a first input signal and a second input signal and an output for providing a high speed output signal, wherein the first input signal is a reference voltage or a high speed signal and the second input signal is a high speed signal. The amplifying circuit further includes a first transmission gate and a second transmission gate coupled in series between the non-inverting input and an inverting input that are enabled during the offset calibration mode. A benefit of this approach is that capacitance between the inverting and non-inverting inputs is reduced by the first and second transmission gates being in series. There is further benefit in reducing this capacitance by having each transmission gate receive an enable signal from a different source.

摘要翻译： 放大电路具有偏移校准模式和正常模式。 放大电路包括具有非反相输入和反相输入的放大器，用于在正常模式期间接收第一输入信号和第二输入信号以及用于提供高速输出信号的输出，其中第一输入信号为 参考电压或高速信号，第二输入信号是高速信号。 放大电路还包括在非反相输入端和反相输入端之间串联耦合的第一传输门极和第二传输栅极，其在偏移校准模式期间被使能。 该方法的优点在于，反相和非反相输入之间的电容由第一和第二传输门串联而减小。 通过使每个传输门从不同的源接收使能信号来减小该电容还有另一个好处。

公开(公告)号：US20100308912A1

公开(公告)日：2010-12-09

申请号：US12479140

申请日：2009-06-05

申请人： Joshua Siegel ,  Hector Sanchez

发明人： Joshua Siegel ,  Hector Sanchez

IPC分类号： H03F3/45

CPC分类号： H03F3/45968 ,  H03F2203/45048

摘要： An amplifying circuit has an offset calibration mode and a normal mode. The amplifying circuit includes an amplifier having a non-inverting input and an inverting input for receiving, during the normal mode, a first input signal and a second input signal and an output for providing a high speed output signal, wherein the first input signal is a reference voltage or a high speed signal and the second input signal is a high speed signal. The amplifying circuit further includes a first transmission gate and a second transmission gate coupled in series between the non-inverting input and an inverting input that are enabled during the offset calibration mode. A benefit of this approach is that capacitance between the inverting and non-inverting inputs is reduced by the first and second transmission gates being in series. There is further benefit in reducing this capacitance by having each transmission gate receive an enable signal from a different source.

摘要翻译： 放大电路具有偏移校准模式和正常模式。 放大电路包括具有非反相输入和反相输入的放大器，用于在正常模式期间接收第一输入信号和第二输入信号以及用于提供高速输出信号的输出，其中第一输入信号为 参考电压或高速信号，第二输入信号是高速信号。 放大电路还包括在非反相输入端和反相输入端之间串联耦合的第一传输门极和第二传输栅极，其在偏移校准模式期间被使能。 该方法的优点在于，反相和非反相输入之间的电容由第一和第二传输门串联而减小。 通过使每个传输门从不同的源接收使能信号来减小该电容还有另一个好处。

公开(公告)号：US5896045A

公开(公告)日：1999-04-20

申请号：US851261

申请日：1997-05-05

申请人： Joshua Siegel ,  Hector Sanchez ,  Chai-Chin Chao

发明人： Joshua Siegel ,  Hector Sanchez ,  Chai-Chin Chao

IPC分类号： H03K19/0185 ,  H03K19/094

CPC分类号： H03K19/018521

摘要： Level shifting circuit (36) utilizes self-timed pulse generators (40, 46) to provide a series of pulses in response to an input signal. The pulses are used to create a pulse of specified duration at a predetermined voltage level at first and second nodes (44, 45). In response to the predetermined pulses, shifted inverters (50, 52) provide a voltage output of either V.sub.DDH or V.sub.DDL, one of two different voltages which exist in a system utilizing the level shifter (36). In one form, level shifting circuit (36) may be used in an output buffer (60) to interface an integrated circuit designed to operate at a low supply voltage with additional integrated circuits operating at a higher supply voltage which could damage the gate oxide of the transistors in the low supply voltage integrated circuit.

摘要翻译： 电平移位电路（36）利用自定时脉冲发生器（40,46）响应于输入信号提供一系列脉冲。 所述脉冲用于在第一和第二节点（44,45）处以预定电压电平创建指定持续时间的脉冲。 响应于预定脉冲，移位的反相器（50,52）提供VDDH或VDDL的电压输出，其中存在于利用电平转换器（36）的系统中存在两个不同电压之一。 在一种形式中，电平移位电路（36）可以用在输出缓冲器（60）中，以将设计为在低电源电压下操作的集成电路与在较高电源电压下工作的附加集成电路进行接口，该集成电路可能损坏栅极氧化物 低电压集成电路中的晶体管。

公开(公告)号：US20240249318A1

公开(公告)日：2024-07-25

申请号：US18420546

申请日：2024-01-23

申请人： Evan Spiegel ,  Robert Cornelius Murphy ,  Celia Nicole Mourkogiannis ,  Edward Mata ,  Eitan Pilipski ,  Jacob Andreou ,  Jackie Assa ,  Joshua Siegel ,  Nima Khajehnouri ,  Steven Hwang ,  Daniel Moreno ,  Jacob Catalano ,  Charles Melbye

发明人： Evan Spiegel ,  Robert Cornelius Murphy ,  Celia Nicole Mourkogiannis ,  Edward Mata ,  Eitan Pilipski ,  Jacob Andreou ,  Jackie Assa ,  Joshua Siegel ,  Nima Khajehnouri ,  Steven Hwang ,  Daniel Moreno ,  Jacob Catalano ,  Charles Melbye

IPC分类号： G06Q30/0251 ,  G06Q30/0241 ,  H04L51/02

CPC分类号： G06Q30/0257 ,  G06Q30/0277 ,  H04L51/02

摘要： A system and method for determining user intent and providing targeted advertising using chatbot interactions is disclosed. The system receives user prompts during chat sessions with a chatbot and generates responses using a large language model. User intent is extracted by analyzing the chat conversations using natural language processing and machine learning techniques. The extracted user intent, comprising weighted keywords and concepts, is used to create a user intent profile. Targeted advertising content is generated based on the user intent profile and provided to the user during subsequent platform interactions. The large language model is continuously retrained using user engagement data to improve intent modeling accuracy. User privacy is maintained by limiting context extraction to chatbot conversations. The system enables personalized and relevant advertising by inferring user intent through conversational interactions.

公开(公告)号：US09081860B2

公开(公告)日：2015-07-14

申请号：US12546508

申请日：2009-08-24

申请人： Phil Genera ,  Joshua Siegel

发明人： Phil Genera ,  Joshua Siegel

IPC分类号： G06F7/00 ,  G06F17/30

CPC分类号： G06F17/3087 ,  G06F17/30241 ,  G06F17/30867

摘要： A computer-implemented location determination method is disclosed. The method includes initiating, on computing device, a native application that provides data storage and data synchronization with a remote server; receiving a call to the native application from an application running within a browser on the device; and providing information indicating a location of the device in response to the call.

摘要翻译： 公开了一种计算机实现的位置确定方法。 该方法包括在计算设备上启动与远程服务器提供数据存储和数据同步的本机应用程序; 从在设备上的浏览器内运行的应用接收到本地应用的呼叫; 以及提供指示响应于该呼叫的设备的位置的信息。

公开(公告)号：US6040729A

公开(公告)日：2000-03-21

申请号：US917306

申请日：1997-08-25

申请人： Hector Sanchez ,  Jose M. Alvarez ,  Joshua Siegel ,  Carmine Nicoletta

发明人： Hector Sanchez ,  Jose M. Alvarez ,  Joshua Siegel ,  Carmine Nicoletta

IPC分类号： H03K19/003 ,  H03K17/687

CPC分类号： H03K19/00384 ,  H03K19/00315

摘要： An output buffer translates digital input signals which toggle between ground and V.sub.DDL to signals which toggle between ground and V.sub.DDH. The technology dielectric breakdown voltage limit is less than the magnitude of V.sub.DDH, such that use of a traditional output stage would subject transistors' dielectrics to voltages which exceed their dielectric breakdown limit, and would thus be damaged. Predrive circuits (40, 50) control output stage (70) transistors' (72, 78) gates, and voltage dropping circuits control output stage (70) transistors (74, 76). These control signals are generated specifically to maximize output stage transistor drive strengths, thereby minimizing output stage size. Output buffer functions when V.sub.DDL =V.sub.DDH, and its performance is V.sub.DDL independent. Temperature compensation is incorporated into the output buffer by deliberately offsetting temperature effects on output stage transistor drive strengths. Desired performance and temperature compensation are accomplished without subjecting any dielectrics to voltages which exceed the technology dielectric breakdown limit.

摘要翻译： 输出缓冲器将数字输入信号转换为在地和VDDL之间切换的接地和VDDH之间的信号。 技术介电击穿电压极限小于VDDH的大小，因此使用传统的输出级将使晶体管的电介质受到超过其介电击穿极限的电压，从而将被损坏。 预驱动电路（40,50）控制输出级（70）晶体管（72,78）门，并且降压电路控制输出级（70）晶体管（74,76）。 专门生成这些控制信号以使输出级晶体管驱动强度最大化，从而使输出级大小最小化。 VDDL = VDDH时的输出缓冲器功能，其性能与VDDL无关。 温度补偿通过故意抵消输出级晶体管驱动强度的温度影响而被并入输出缓冲器。 实现所需的性能和温度补偿，而不会对任何电介质施加超过技术介电击穿极限的电压。

公开(公告)号：US5917358A

公开(公告)日：1999-06-29

申请号：US987361

申请日：1997-12-09

申请人： Hector Sanchez ,  Carmine Nicoletta ,  Joshua Siegel ,  Jose Alvarez

发明人： Hector Sanchez ,  Carmine Nicoletta ,  Joshua Siegel ,  Jose Alvarez

IPC分类号： H03K19/0185 ,  H03L5/00

CPC分类号： H03K19/018585

摘要： Output buffer (100) translates input signals from one voltage range to a second voltage range. The second voltage range may be identical to the first range or may be greater. The particular range is programmable by one of several ways. This feature makes output buffer especially suitable for use in devices which must be compatible with two voltage ranges. Output buffer uses a bias generator (110) to limit the voltage across the gate oxide of its various transistors to a level which is consistent with the first voltage range.

摘要翻译： 输出缓冲器（100）将输入信号从一个电压范围转换到第二电压范围。 第二电压范围可以与第一范围相同或者可以更大。 特定范围可以通过几种方式之一进行编程。 该功能使输出缓冲器特别适用于必须兼容两个电压范围的器件。 输出缓冲器使用偏置发生器（110）将其各种晶体管的栅极氧化物上的电压限制到与第一电压范围一致的水平。

公开(公告)号：US07872494B2

公开(公告)日：2011-01-18

申请号：US12483386

申请日：2009-06-12

申请人： James A. Welker ,  Hector Sanchez ,  Joshua Siegel

发明人： James A. Welker ,  Hector Sanchez ,  Joshua Siegel

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K5/1565 ,  H04L25/0298 ,  H04L25/08

摘要： Components of a memory controller are calibrated in a select sequence to compensate for variances in skew and signal level variations. The offset bias of the receiver of the I/O cell and the termination resistance of the I/O cell are calibrated. The duty cycles of the transmit path and receive path associated with the I/O cell can be calibrated using the calibrated receiver. In one aspect, the driver of the I/O cell can be calibrated prior to calibrating the receiver. Performing the calibration processes of the memory controller in one of the particular sequences described herein improves the timing budgets for the signaling conducted by the memory controller.

摘要翻译： 存储器控制器的组件以选择顺序校准，以补偿偏斜和信号电平变化的方差。 校准I / O单元的接收器的偏移偏移和I / O单元的终端电阻。 可以使用校准的接收器校准与I / O单元相关联的发送路径和接收路径的占空比。 在一个方面，可以在校准接收器之前校准I / O单元的驱动器。 以本文描述的特定序列之一执行存储器控制器的校准过程改进了由存储器控制器进行的信令的定时预算。

公开(公告)号：US20090018655A1

公开(公告)日：2009-01-15

申请号：US11777733

申请日：2007-07-13

申请人： John Brunelle ,  Joshua Siegel ,  Christine Nguyen ,  Brenda Yantzer ,  Thomas Sander

发明人： John Brunelle ,  Joshua Siegel ,  Christine Nguyen ,  Brenda Yantzer ,  Thomas Sander

IPC分类号： A61F2/08

CPC分类号： A61F2/0059 ,  A61B17/06166 ,  A61B17/1128 ,  A61B2017/0464 ,  A61F2/0077 ,  A61F2/08 ,  A61L27/24

摘要： Disclosed are biocompatible implants that combine a scaffold material for supporting long term repair of a soft tissue with an elongated member such as a suture for aiding in placement of the scaffold during a surgical procedure as well as for immediate mechanical reinforcement of a repair site. The components of an implant are combined such that a longitudinal load placed upon a composite structure can be borne primarily by the elongated member and the scaffold material is isolated from the longitudinal load. Thus, the scaffold material of a composite can be protected from damage due to applied loads and stresses during and following a surgical procedure.

摘要翻译： 公开了生物相容性植入物，其将用于支撑软组织的长期修复的支架材料与诸如缝合线的细长构件组合以帮助在外科手术过程中放置​​支架以及立即机械加固修复部位。 组合植入物的组分使得放置在复合结构上的纵向载荷主要由细长构件承载，并且支架材料与纵向载荷隔离。 因此，复合材料的支架材料可以在外科手术期间和之后由于施加的负荷和应力而被保护免受损伤。