公开(公告)号：US20140062451A1

公开(公告)日：2014-03-06

申请号：US13605662

申请日：2012-09-06

申请人： JOSHUA SIEGEL ,  Khoi B. Mai

发明人： JOSHUA SIEGEL ,  Khoi B. Mai

IPC分类号： G05F3/16

CPC分类号： G05F3/30

摘要： A band gap reference circuit including a band gap reference generator having an output for providing a reference voltage and a startup circuit for controlling current provided to the band gap reference generator when activated. The startup circuit includes a turnoff circuit having an output to deactivate the startup circuit to not control current to the band gap reference generator based on a voltage of the output of the band gap reference generator. The turnoff circuit includes an inverter having a first transistor of a first conductivity type in series with a second transistor of a second conductivity type opposite the first conductivity type. The startup circuit includes a body bias circuit connected to a body of the first transistor to provide a voltage differential between the body of the first transistor and a source terminal of the first transistor.

摘要翻译： 一种带隙参考电路，包括具有用于提供参考电压的输出的带隙基准发生器和用于当被激活时控制提供给带隙基准发生器的电流的启动电路。 启动电路包括具有输出的开关电路，该输出用于基于带隙基准发生器的输出的电压来停止启动电路以不控制到带隙基准发生器的电流。 所述截止电路包括具有与第一导电类型相反的第二导电类型的第二晶体管串联的第一导电类型的第一晶体管的反相器。 启动电路包括连接到第一晶体管的主体的主体偏置电路，以在第一晶体管的主体和第一晶体管的源极之间提供电压差。

公开(公告)号：US07893741B2

公开(公告)日：2011-02-22

申请号：US12483392

申请日：2009-06-12

申请人： Lipeng Cao ,  Khoi B. Mai ,  Hector Sanchez

发明人： Lipeng Cao ,  Khoi B. Mai ,  Hector Sanchez

IPC分类号： H03L7/00

CPC分类号： H03K5/133 ,  H03K2005/00058 ,  H03K2005/00234

摘要： Signal edge alignment embodiments include multiple delay stages connected in series. Each delay stage includes a delay line, an interface circuit, and a tap selection circuit. The delay line applies fixed-width delays to an input signal to produce delayed versions of the input signal at a plurality of taps. The interface circuit, which is characterized by an inherent interface circuit delay, passes one of the delayed versions to an interface circuit output in response to a control signal. The tap selection circuit determines a finally-identified tap of the plurality of taps by determining an initially-identified tap at which a delayed version of the input signal most closely has a desired alignment with the input signal, and by identifying the finally-identified tap in the control signal as a tap that occurs earlier in the delay line than the initially-identified tap. This compensates for the inherent delay of the delay stage.

摘要翻译： 信号沿对准实施例包括串联连接的多个延迟级。 每个延迟级包括延迟线，接口电路和抽头选择电路。 延迟线将固定宽度延迟施加到输入信号，以在多个抽头处产生输入信号的延迟版本。 其特征在于固有接口电路延迟的接口电路响应于控制信号将延迟版本中的一个传递到接口电路输出。 抽头选择电路通过确定最初识别的抽头来确定多个抽头的最终识别的抽头，其中输入信号的延迟版本最接近地具有与输入信号的期望对准，并且通过识别最终识别的抽头 在控制信号中，作为在延迟线中比最初识别的抽头更早发生的抽头。 这补偿了延迟阶段的固有延迟。

公开(公告)号：US07880550B2

公开(公告)日：2011-02-01

申请号：US12483503

申请日：2009-06-12

申请人： Khoi B. Mai ,  Hector Sanchez

发明人： Khoi B. Mai ,  Hector Sanchez

IPC分类号： H03L7/08 ,  H03L7/099

CPC分类号： H03L7/099

摘要： Apparatus are provided for a voltage-controlled oscillator module. A voltage-controlled oscillator module comprises an input node for receiving an input voltage, a voltage-controlled oscillator, and voltage translation circuitry coupled between the input node and the voltage-controlled oscillator. The voltage translation circuitry is configured to generate a control voltage based on the input voltage and the voltage-controlled oscillator generates an oscillating signal at an oscillation frequency in response to the control voltage. Biasing circuitry is coupled to the voltage translation circuitry, and the biasing circuitry is configured to adjust the ratio of the control voltage to the input voltage.

摘要翻译： 提供用于压控振荡器模块的装置。 压控振荡器模块包括用于接收输入电压的输入节点，压控振荡器和耦合在输入节点和压控振荡器之间的电压转换电路。 电压转换电路被配置为基于输入电压产生控制电压，并且压控振荡器响应于控制电压产生振荡频率的振荡信号。 偏置电路耦合到电压转换电路，并且偏置电路被配置为调节控制电压与输入电压的比率。

公开(公告)号：US09110486B2

公开(公告)日：2015-08-18

申请号：US13605662

申请日：2012-09-06

申请人： Joshua Siegel ,  Khoi B. Mai

发明人： Joshua Siegel ,  Khoi B. Mai

IPC分类号： G05F3/30

CPC分类号： G05F3/30

摘要： A band gap reference circuit including a band gap reference generator having an output for providing a reference voltage and a startup circuit for controlling current provided to the band gap reference generator when activated. The startup circuit includes a turnoff circuit having an output to deactivate the startup circuit to not control current to the band gap reference generator based on a voltage of the output of the band gap reference generator. The turnoff circuit includes an inverter having a first transistor of a first conductivity type in series with a second transistor of a second conductivity type opposite the first conductivity type. The startup circuit includes a body bias circuit connected to a body of the first transistor to provide a voltage differential between the body of the first transistor and a source terminal of the first transistor.

摘要翻译： 一种带隙参考电路，包括具有用于提供参考电压的输出的带隙基准发生器和用于当被激活时控制提供给带隙基准发生器的电流的启动电路。 启动电路包括具有输出的开关电路，该输出用于基于带隙基准发生器的输出的电压来停止启动电路以不控制到带隙基准发生器的电流。 所述截止电路包括具有与第一导电类型相反的第二导电类型的第二晶体管串联的第一导电类型的第一晶体管的反相器。 启动电路包括连接到第一晶体管的主体的主体偏置电路，以在第一晶体管的主体和第一晶体管的源极之间提供电压差。

公开(公告)号：US20100315141A1

公开(公告)日：2010-12-16

申请号：US12483392

申请日：2009-06-12

申请人： Lipeng Cao ,  Khoi B. Mai ,  Hector Sanchez

发明人： Lipeng Cao ,  Khoi B. Mai ,  Hector Sanchez

IPC分类号： H03L7/00

CPC分类号： H03K5/133 ,  H03K2005/00058 ,  H03K2005/00234

摘要： Signal edge alignment embodiments include multiple delay stages connected in series. Each delay stage includes a delay line, an interface circuit, and a tap selection circuit. The delay line applies fixed-width delays to an input signal to produce delayed versions of the input signal at a plurality of taps. The interface circuit, which is characterized by an inherent interface circuit delay, passes one of the delayed versions to an interface circuit output in response to a control signal. The tap selection circuit determines a finally-identified tap of the plurality of taps by determining an initially-identified tap at which a delayed version of the input signal most closely has a desired alignment with the input signal, and by identifying the finally-identified tap in the control signal as a tap that occurs earlier in the delay line than the initially-identified tap. This compensates for the inherent delay of the delay stage.

摘要翻译： 信号沿对准实施例包括串联连接的多个延迟级。 每个延迟级包括延迟线，接口电路和抽头选择电路。 延迟线将固定宽度延迟施加到输入信号，以在多个抽头处产生输入信号的延迟版本。 其特征在于固有接口电路延迟的接口电路响应于控制信号将延迟版本中的一个传递到接口电路输出。 抽头选择电路通过确定最初识别的抽头来确定多个抽头的最终识别的抽头，其中输入信号的延迟版本最接近地具有与输入信号的期望对准，并且通过识别最终识别的抽头 在控制信号中，作为在延迟线中比最初识别的抽头更早发生的抽头。 这补偿了延迟阶段的固有延迟。

公开(公告)号：US09909934B2

公开(公告)日：2018-03-06

申请号：US14194105

申请日：2014-02-28

申请人： Jose A. Camarena ,  Khoi B. Mai ,  Dale J. McQuirk

发明人： Jose A. Camarena ,  Khoi B. Mai ,  Dale J. McQuirk

IPC分类号： G01K7/01 ,  G01K15/00 ,  G01K3/00

CPC分类号： G01K15/005 ,  G01K3/005 ,  G01K7/01

摘要： A determination is made if a temperature of a system has exceeded a hot threshold or a cold threshold. At room temperature, a first adjustment is determined for first nominal settings. The first nominal settings are for a first input to a first comparator. At room temperature, a second adjustment is determined for second nominal settings. The second nominal settings are for a first input to a second comparator. The temperature is monitored, during normal operation of the system, using a temperature dependent voltage with the first comparator adjusted with the first adjustment and second comparator adjusted with the second adjustment.

公开(公告)号：US20150247764A1

公开(公告)日：2015-09-03

申请号：US14194105

申请日：2014-02-28

申请人： JOSE A. CAMARENA ,  Khoi B. Mai ,  Dale J. McQuirk

发明人： JOSE A. CAMARENA ,  Khoi B. Mai ,  Dale J. McQuirk

IPC分类号： G01K15/00 ,  G01K7/01

CPC分类号： G01K15/005 ,  G01K3/005 ,  G01K7/01

摘要： A determination is made if a temperature of a system has exceeded a hot threshold or a cold threshold. At room temperature, a first adjustment is determined for first nominal settings. The first nominal settings are for a first input to a first comparator. At room temperature, a second adjustment is determined for second nominal settings. The second nominal settings are for a first input to a second comparator. The temperature is monitored, during normal operation of the system, using a temperature dependent voltage with the first comparator adjusted with the first adjustment and second comparator adjusted with the second adjustment.

摘要翻译： 如果系统的温度已经超过热阈值或冷阈值，则确定。 在室温下，对于第一标称设置确定第一次调整。 第一个标称设置用于第一个比较器的第一个输入。 在室温下，对于第二标称设置确定第二调整。 第二个标称设置用于第二个比较器的第一个输入。 在系统正常运行期间，使用温度依赖电压监测温度，第一个比较器通过第一次调整进行调整，第二个比较器通过第二次调整进行调整。

公开(公告)号：US07221188B2

公开(公告)日：2007-05-22

申请号：US10967563

申请日：2004-10-18

申请人： Andrew A. Bjorksten ,  Khoi B. Mai ,  Paul C. Rossbach

发明人： Andrew A. Bjorksten ,  Khoi B. Mai ,  Paul C. Rossbach

IPC分类号： H03K19/096

CPC分类号： H03K19/0963

摘要： A logic circuit including at least one evaluate circuit coupled to a static output logic circuit. In one example, the evaluate circuit includes a dynamic node, a full keeper, an evaluate device, and a logic tree. In some examples, the output logic circuit is a sampled static output logic circuit and includes a sample device. In some examples, the logic circuit includes multiple evaluate circuits, each with a dynamic node coupled to a control gate of a transistor of the output logic circuit. Some examples may include a delay in a clock signal to increase the internal race margin.

摘要翻译： 逻辑电路，包括耦合到静态输出逻辑电路的至少一个评估电路。 在一个示例中，评估电路包括动态节点，完整守护者，评估设备和逻辑树。 在一些示例中，输出逻辑电路是采样静态输出逻辑电路，并且包括采样器件。 在一些示例中，逻辑电路包括多个评估电路，每个评估电路具有耦合到输出逻辑电路的晶体管的控制栅极的动态节点。 一些示例可以包括时钟信号的延迟以增加内部游隙。