公开(公告)号：US20080113511A1

公开(公告)日：2008-05-15

申请号：US11730264

申请日：2007-03-30

Applicant: Sang-joon Park ,  Yong-hyun Kwon ,  Jun Seo ,  Sung-il Cho ,  Chang-jin Kang ,  Jae-kyu Ha

Inventor： Sang-joon Park ,  Yong-hyun Kwon ,  Jun Seo ,  Sung-il Cho ,  Chang-jin Kang ,  Jae-kyu Ha

IPC: H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897

Abstract: A double pattern method of forming a plurality of contact holes in a material layer formed on a substrate is disclosed. The method forms a parallel plurality of first hard mask patterns separated by a first pitch in a first direction on the material layer, a self-aligned parallel plurality of second hard mask patterns interleaved with the first hard mask patterns and separated from the first hard mask patterns by a buffer layer to form composite mask patterns, and a plurality of upper mask patterns in a second direction intersecting the first direction to mask selected portions of the buffer layer in conjunction with the composite mask patterns. The method then etches non-selected portions of the buffer layer using the composite hard mask patterns and the upper mask patterns as an etch mask to form a plurality of hard mask holes exposing selected portions of the material layer, and then etches the selected portions of the material layer to form the plurality of contact holes.

Abstract translation: 公开了一种在形成在基板上的材料层中形成多个接触孔的双重图案方法。 该方法形成在材料层上沿第一方向以第一间距分开的平行多个第一硬掩模图案，与第一硬掩模图案交错并与第一硬掩模分离的自对准并行多个第二硬掩模图案 通过缓冲层形成图案以形成复合掩模图案，以及与第一方向相交的第二方向的多个上掩模图案，以与复合掩模图案一起掩蔽缓冲层的选定部分。 然后，该方法使用复合硬掩模图案和上掩模图案作为蚀刻掩模蚀刻缓冲层的未选择部分，以形成暴露材料层的选定部分的多个硬掩模孔，然后蚀刻所选择的部分 所述材料层形成所述多个接触孔。

公开(公告)号：US07235445B2

公开(公告)日：2007-06-26

申请号：US11148760

申请日：2005-06-09

Applicant: Jae-Kyu Ha ,  Jong-Chul Park

Inventor： Jae-Kyu Ha ,  Jong-Chul Park

IPC: H01L21/336

CPC classification number: H01L29/66621 ,  H01L21/823437 ,  H01L27/10876

Abstract: Methods are provided for forming a device, such as a semiconductor device. A field region and an active region of a substrate are defined in which the field region has an upper surface that extends further away from the substrate and is higher than an upper surface of the active region. A hard mask layer is formed with a substantially planar upper surface on the field region and the active region. The hard mask layer is partially etched to form a hard mask pattern that exposes at least a portion of the active region. The substrate is partially etched in the active region using the hard mask pattern as an etching mask to form a gate trench. A recessed gate electrode if formed on the substrate in the gate trench.

Abstract translation: 提供了用于形成诸如半导体器件的器件的方法。 定义了场区域和衬底的有源区域，其中场区域具有远离衬底延伸的上表面并且高于有源区域的上表面。 硬掩模层在场区域和有源区域上形成有基本平坦的上表面。 硬掩模层被部分蚀刻以形成暴露至少一部分有源区的硬掩模图案。 使用硬掩模图案作为蚀刻掩模在有源区中部分地蚀刻衬底以形成栅极沟槽。 如果形成在栅极沟槽中的衬底上的凹陷栅电极。

公开(公告)号：US07534704B2

公开(公告)日：2009-05-19

申请号：US11449839

申请日：2006-06-09

Applicant: Jae-Kyu Ha ,  Jun Seo ,  Min-Chul Chae ,  Yong-Sun Ko ,  Young-Mi Lee ,  Jae-Seung Hwang

Inventor： Jae-Kyu Ha ,  Jun Seo ,  Min-Chul Chae ,  Yong-Sun Ko ,  Young-Mi Lee ,  Jae-Seung Hwang

IPC: H01L21/20

CPC classification number: H01L21/84 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/02667 ,  H01L21/76262 ,  H01L27/1203

Abstract: In a thin layer structure and a method of forming the same, a first preliminary insulation pattern is formed on a substrate and includes a first opening exposing the substrate. One or more preliminary seed patterns including single crystalline silicon are formed in the first opening. A second insulation layer is formed on the first preliminary insulation pattern and the one or more preliminary seed patterns. A second insulation pattern, a first insulation pattern and one or more seed patterns are formed by etching the first and second insulation layers and the one or more preliminary seed patterns. The second insulation pattern includes a second opening having a flat bottom portion. A single crystalline silicon pattern is formed in the second opening, wherein a central thickness of the single crystalline silicon pattern is substantially identical to a peripheral thickness thereof, thereby reducing or preventing a thinning defect in a semiconductor device.

Abstract translation: 在薄层结构及其形成方法中，在基板上形成第一预备绝缘图案，并且包括暴露基板的第一开口。 在第一开口中形成包括单晶硅的一种或多种初步种子图案。 在第一预备绝缘图案和一个或多个初步种子图案上形成第二绝缘层。 通过蚀刻第一和第二绝缘层和一个或多个初步种子图案来形成第二绝缘图案，第一绝缘图案和一个或多个种子图案。 第二绝缘图案包括具有平坦底部的第二开口。 在第二开口中形成单晶硅图案，其中单晶硅图案的中心厚度与其周边厚度基本相同，从而减少或防止半导体器件中的变薄缺陷。

公开(公告)号：US20050230734A1

公开(公告)日：2005-10-20

申请号：US11109422

申请日：2005-04-19

Applicant: Jae-Kyu Ha ,  Jong-Chul Park

Inventor： Jae-Kyu Ha ,  Jong-Chul Park

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/76 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L27/10817 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876

Abstract: Embodiments of the invention include dynamic random access memory (DRAM) devices that utilize field effect transistors with trench-based gate electrodes. In these devices, a semiconductor substrate is provided having an isolation trench therein. This isolation trench is formed in a first portion of the semiconductor substrate. An electrically insulating liner is provided on a bottom and sidewalls of the isolation trench. The isolation trench is also filled with field oxide region, which extends on the electrically insulating liner. A field effect transistor is also provided in the semiconductor substrate. This transistor includes a gate electrode trench in a second portion of the semiconductor substrate and a gate insulating layer that lines a bottom and sidewalls of the gate electrode trench. A gate electrode is provided in the gate electrode trench. The gate electrode contacts the electrically insulating liner in the isolation trench and the gate insulating layer. Source and drain regions extend in the semiconductor substrate and adjacent the gate electrode.

Abstract translation: 本发明的实施例包括使用具有基于沟槽的栅电极的场效应晶体管的动态随机存取存储器（DRAM）器件。 在这些器件中，提供了在其中具有隔离沟槽的半导体衬底。 该隔离沟槽形成在半导体衬底的第一部分中。 电绝缘衬垫设置在隔离沟槽的底部和侧壁上。 隔离沟槽还填充有在电绝缘衬垫上延伸的场氧化物区域。 在半导体衬底中还提供场效应晶体管。 该晶体管包括在半导体衬底的第二部分中的栅极电极沟槽和对栅极电极沟槽的底部和侧壁进行排列的栅极绝缘层。 栅电极设置在栅电极沟槽中。 栅电极接触隔离沟槽和栅极绝缘层中的电绝缘衬垫。 源极和漏极区域在半导体衬底中延伸并且与栅电极相邻。

公开(公告)号：US20060286298A1

公开(公告)日：2006-12-21

申请号：US11449839

申请日：2006-06-09

Applicant: Jae-Kyu Ha ,  Jun Seo ,  Min-Chul Chae ,  Yong-Sun Ko ,  Young-Mi Lee ,  Jae-Seung Hwang

Inventor： Jae-Kyu Ha ,  Jun Seo ,  Min-Chul Chae ,  Yong-Sun Ko ,  Young-Mi Lee ,  Jae-Seung Hwang

IPC: B05D5/00

CPC classification number: H01L21/84 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/02667 ,  H01L21/76262 ,  H01L27/1203

Abstract: In a thin layer structure and a method of forming the same, a first preliminary insulation pattern is formed on a substrate and includes a first opening exposing the substrate. One or more preliminary seed patterns including single crystalline silicon are formed in the first opening. A second insulation layer is formed on the first preliminary insulation pattern and the one or more preliminary seed patterns. A second insulation pattern, a first insulation pattern and one or more seed patterns are formed by etching the first and second insulation layers and the one or more preliminary seed patterns. The second insulation pattern includes a second opening having a flat bottom portion. A single crystalline silicon pattern is formed in the second opening, wherein a central thickness of the single crystalline silicon pattern is substantially identical to a peripheral thickness thereof, thereby reducing or preventing a thinning defect in a semiconductor device.

公开(公告)号：US20050277254A1

公开(公告)日：2005-12-15

申请号：US11148760

申请日：2005-06-09

Applicant: Jae-Kyu Ha ,  Jong-Chul Park

Inventor： Jae-Kyu Ha ,  Jong-Chul Park

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/8234 ,  H01L21/8242

CPC classification number: H01L29/66621 ,  H01L21/823437 ,  H01L27/10876

Abstract: Methods are provided for forming a device, such as a semiconductor device. A field region and an active region of a substrate are defined in which the field region has an upper surface that extends further away from the substrate and is higher than an upper surface of the active region. A hard mask layer is formed with a substantially planar upper surface on the field region and the active region. The hard mask layer is partially etched to form a hard mask pattern that exposes at least a portion of the active region. The substrate is partially etched in the active region using the hard mask pattern as an etching mask to form a gate trench. A recessed gate electrode if formed on the substrate in the gate trench.

Abstract translation: 提供了用于形成诸如半导体器件的器件的方法。 定义了场区域和衬底的有源区域，其中场区域具有远离衬底延伸的上表面并且高于有源区域的上表面。 硬掩模层在场区域和有源区域上形成有基本平坦的上表面。 硬掩模层被部分蚀刻以形成暴露至少一部分有源区的硬掩模图案。 使用硬掩模图案作为蚀刻掩模在有源区中部分地蚀刻衬底以形成栅极沟槽。 如果形成在栅极沟槽中的衬底上的凹陷栅电极。

公开(公告)号：US07531449B2

公开(公告)日：2009-05-12

申请号：US11730264

申请日：2007-03-30

Applicant: Sang-joon Park ,  Yong-hyun Kwon ,  Jun Seo ,  Sung-il Cho ,  Chang-jin Kang ,  Jae-kyu Ha

Inventor： Sang-joon Park ,  Yong-hyun Kwon ,  Jun Seo ,  Sung-il Cho ,  Chang-jin Kang ,  Jae-kyu Ha

IPC: H01L21/4763

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897

Abstract: A double pattern method of forming a plurality of contact holes in a material layer formed on a substrate is disclosed. The method forms a parallel plurality of first hard mask patterns separated by a first pitch in a first direction on the material layer, a self-aligned parallel plurality of second hard mask patterns interleaved with the first hard mask patterns and separated from the first hard mask patterns by a buffer layer to form composite mask patterns, and a plurality of upper mask patterns in a second direction intersecting the first direction to mask selected portions of the buffer layer in conjunction with the composite mask patterns. The method then etches non-selected portions of the buffer layer using the composite hard mask patterns and the upper mask patterns as an etch mask to form a plurality of hard mask holes exposing selected portions of the material layer, and then etches the selected portions of the material layer to form the plurality of contact holes.

Abstract translation: 公开了一种在形成在基板上的材料层中形成多个接触孔的双重图案方法。 该方法形成在材料层上沿第一方向以第一间距分开的平行多个第一硬掩模图案，与第一硬掩模图案交错并与第一硬掩模分离的自对准并行多个第二硬掩模图案 通过缓冲层形成图案以形成复合掩模图案，以及与第一方向相交的第二方向的多个上掩模图案，以与复合掩模图案一起掩蔽缓冲层的选定部分。 然后，该方法使用复合硬掩模图案和上掩模图案作为蚀刻掩模蚀刻缓冲层的未选择部分，以形成暴露材料层的选定部分的多个硬掩模孔，然后蚀刻所选择的部分 所述材料层形成所述多个接触孔。