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3 条记录 (耗时 0.012 秒)

    Signal edge trimmer circuit
    1.
    发明授权
    Signal edge trimmer circuit 失效
    信号边缘微调电路

    公开(公告)号：US4823024A

    公开(公告)日：1989-04-18

    申请号：US212833

    申请日：1988-06-29

    申请人： Ikuo J. Sanwo ,  James A. Donahue ,  Donald G. Tipon

    发明人： Ikuo J. Sanwo ,  James A. Donahue ,  Donald G. Tipon

    IPC分类号： H03K5/00 ,  H03K5/04 ,  H03K5/13 ,  H03K3/01 ,  H03K17/56 ,  H03K17/687

    CPC分类号： H03K5/133 ,  H03K5/04 ,  H03K2005/00195

    摘要： A MOS circuit for trimming a digital pulse signal by delaying the rising edge of the pulse signal for a predetermined period of time and passing the falling edge without delay. The circuit includes two MOS output transistors and a signal buffer. The signal buffer has a number of stages for delaying the pulse signal, with the number chosen to control the delay in the rising edge of the pulse signal. One of the output transistors receives the pulse signal at its drain and is enabled by the delayed pulse signal from the signal buffer to pass the pulse signal after the predetermined period of time to its source at the output of the circuit, so that the rising edge is delayed, but the falling edge is not. The other output transistor is enabled to ground the output of the circuit after the falling edge of the pulse signal. A self-booting circuit drives the gate of the one output transistor to assure that the voltage level of the trimmed signal will not be reduced by dissipation across the transistor.

    摘要翻译： MOS电路，用于通过将脉冲信号的上升沿延迟预定时间段并且不延迟地通过下降沿来修整数字脉冲信号。 该电路包括两个MOS输出晶体管和一个信号缓冲器。 信号缓冲器具有用于延迟脉冲信号的多个级，其中选择的数字用于控制脉冲信号的上升沿中的延迟。 输出晶体管中的一个在其漏极接收脉冲信号，并且通过来自信号缓冲器的延迟脉冲信号使其能够在预定时间段之后将脉冲信号传递到电路输出端的源极，使得上升沿 是延迟，但下降的边缘不是。 在脉冲信号的下降沿之后，另一个输出晶体管使能电路的输出。 自引导电路驱动一个输出晶体管的栅极，以确保修整信号的电压电平不会由于跨越晶体管的耗散而减小。

    High speed CMOS backpanel transceiver
    2.
    发明授权
    High speed CMOS backpanel transceiver 失效
    高速CMOS背板收发器

    公开(公告)号：US5019728A

    公开(公告)日：1991-05-28

    申请号：US580017

    申请日：1990-09-10

    申请人： Ikuo J. Sanwo ,  James A. Donahue

    发明人： Ikuo J. Sanwo ,  James A. Donahue

    IPC分类号： G06F3/00 ,  H03K19/0185

    CPC分类号： H03K19/018528 ,  H03K19/018592

    摘要： In a high speed complementary metal-oxide-semiconductor (CMOS) inter-integrated circuit (IC) chip communication system, transmission line voltage swings between logic high and logic low levels are reduced by defining minimum and maximum bus voltages which lie between CMOS logic levels, thus lowering bus transition and hence data transfer times. The system is versatile, and does not involve typical emitter-coupled logic (ECL) logic levels. Transceivers interfacing between IC chips and the backpanel transmit data in the reduced logic level range on a pre-charged transmission line, and receive and convert data back to CMOS levels. A limiting transistor in the transmitter portion of the transceiver limits logic low level of the transmission line. The receiver portion of the transceiver converts the voltages received to CMOS levels with the aid of a differential (sense) amplifier.

    摘要翻译： 在高速互补金属氧化物半导体（CMOS）集成电路（IC）芯片通信系统中，通过定义位于CMOS逻辑电平之间的最小和最大总线电压来降低逻辑高电平和逻辑低电平之间的传输线电压摆幅 ，从而降低总线转换，从而降低数据传输时间。 该系统是通用的，不涉及典型的发射极耦合逻辑（ECL）逻辑电平。 IC芯片和背板之间的接收器在预充电传输线路上以降低的逻辑电平范围传输数据，并将数据接收并转换回CMOS电平。 收发器的发射器部分中的限制晶体管限制传输线的逻辑低电平。 收发器的接收器部分借助于差分（感测）放大器将接收的电压转换为CMOS电平。