公开(公告)号：US08786105B1

公开(公告)日：2014-07-22

申请号：US13739045

申请日：2013-01-11

Applicant: Thorsten Meyer ,  Sven Albers ,  Christian Geissler ,  Andreas Wolter ,  Markus Brunnbauer ,  David O'Sullivan ,  Frank Zudock ,  Jan Proschwitz

Inventor： Thorsten Meyer ,  Sven Albers ,  Christian Geissler ,  Andreas Wolter ,  Markus Brunnbauer ,  David O'Sullivan ,  Frank Zudock ,  Jan Proschwitz

IPC: H01L23/48 ,  H01L21/00

CPC classification number: H01L23/315 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/562 ,  H01L24/19 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device is described having at least one semiconductor chip, the chip having an active area on a top side thereof, the active area formed at least in part of low-k material, said low-k material defining a low-k subarea of said active area; an embedding material, in which said at least one semiconductor chip is embedded, at least part of the embedding material forming a coplanar area with said active area; at least one contact area within the low-k subarea; a redistribution layer on the coplanar area, the redistribution layer connected to said contact areas; at least one first-level interconnect, located outside said low-k subarea, the first-level interconnect electrically connected to at least one of said contact areas via the redistribution layer.

Abstract translation: 描述了半导体器件，其具有至少一个半导体芯片，该芯片在其顶侧具有有源区，至少部分形成在低k材料上的有源区，所述低k材料限定低k分区 说活跃区; 嵌入材料，其中所述至少一个半导体芯片被嵌入，所述嵌入材料的至少一部分与所述有源区域形成共面区域; 低k子区域内的至少一个接触区域; 在共面区域上的再分配层，再分配层连接到所述接触区域; 位于所述低k子区域外的至少一个第一级互连，所述第一级互连经由再分配层电连接到所述接触区域中的至少一个。

公开(公告)号：US20230282546A1

公开(公告)日：2023-09-07

申请号：US17685496

申请日：2022-03-03

Applicant: Bernd Waidhas ,  Sonja Koller ,  Jan Proschwitz ,  Eduardo De Mesa

Inventor： Bernd Waidhas ,  Sonja Koller ,  Jan Proschwitz ,  Eduardo De Mesa

IPC: H01L23/427 ,  H01L23/367 ,  H01L23/08 ,  H01L23/473 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L23/427 ,  H01L23/3672 ,  H01L23/08 ,  H01L23/473 ,  H01L23/481 ,  H01L21/76877

Abstract: Embodiments of a microelectronic assembly comprise an integrated circuit (IC) die and a package substrate having a core and redistribution layers on either side of the core. The IC die is coupled to a face of the package substrate, the face being parallel to the core. The core comprises one of glass, ceramic, and metal. The redistribution layers comprise one or more layers of a dielectric material, with conductive traces adjacent to the one or more layers of the dielectric material and conductive vias through the one or more layers of the dielectric material. The core comprises a hollow channel.

公开(公告)号：US20140197530A1

公开(公告)日：2014-07-17

申请号：US13739045

申请日：2013-01-11

Applicant: Thorsten Meyer ,  Sven Albers ,  Christian Geissler ,  Andreas Wolter ,  Markus Brunnbauer ,  David O'Sullivan ,  Frank Zudock ,  Jan Proschwitz

Inventor： Thorsten Meyer ,  Sven Albers ,  Christian Geissler ,  Andreas Wolter ,  Markus Brunnbauer ,  David O'Sullivan ,  Frank Zudock ,  Jan Proschwitz

IPC: H01L23/29 ,  H01L21/56

CPC classification number: H01L23/315 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/562 ,  H01L24/19 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device is described having at least one semiconductor chip, the chip having an active area on a top side thereof, the active area formed at least in part of low-k material, said low-k material defining a low-k subarea of said active area; an embedding material, in which said at least one semiconductor chip is embedded, at least part of the embedding material forming a coplanar area with said active area; at least one contact area within the low-k subarea; a redistribution layer on the coplanar area, the redistribution layer connected to said contact areas; at least one first-level interconnect, located outside said low-k subarea, the first-level interconnect electrically connected to at least one of said contact areas via the redistribution layer.

Abstract translation: 描述了半导体器件，其具有至少一个半导体芯片，该芯片在其顶侧具有有源区，至少部分形成在低k材料上的有源区，所述低k材料限定低k分区 说活跃区; 嵌入材料，其中所述至少一个半导体芯片被嵌入，所述嵌入材料的至少一部分与所述有源区域形成共面区域; 低k子区域内的至少一个接触区域; 在共面区域上的再分配层，再分配层连接到所述接触区域; 位于所述低k子区域外的至少一个第一级互连，所述第一级互连经由再分配层电连接到所述接触区域中的至少一个。