公开(公告)号：US5519883A

公开(公告)日：1996-05-21

申请号：US18829

申请日：1993-02-18

申请人： Theodore C. White ,  Chung W. Wong ,  Kha Nguyen ,  Jayesh V. Sheth ,  Craig W. Harris

发明人： Theodore C. White ,  Chung W. Wong ,  Kha Nguyen ,  Jayesh V. Sheth ,  Craig W. Harris

IPC分类号： G06F11/20 ,  G06F13/40 ,  G06F13/00 ,  G06F13/20

CPC分类号： G06F11/2007 ,  G06F13/4027

摘要： An interbus interface module enables storage and transfer of commands, messages and data between parallel a dual system bus operating on a first protocol and a subrequestor bus operating on a second protocol. The interface module serves a first group of requestors, such as multiple processors and main memory, for handling data transfers to and from the subrequestor bus via said dual system buses while also handling data transfers to and from a second group of requestors connected to the subrequestor bus.

摘要翻译： Interbus接口模块能够在并行运行在第一协议上的双系统总线和在第二协议上工作的子请求总线之间存储和传送命令，消息和数据。 接口模块服务第一组请求者，例如多处理器和主存储器，用于经由所述双系统总线处理到和从子请求总线的数据传输，同时还处理到和连接到子请求器的第二组请求者的数据传输 总线。

公开(公告)号：US5293496A

公开(公告)日：1994-03-08

申请号：US3352

申请日：1993-01-12

申请人： Theodore C. White ,  Jayesh V. Sheth ,  Dan T. Tran ,  Paul B. Ricci

发明人： Theodore C. White ,  Jayesh V. Sheth ,  Dan T. Tran ,  Paul B. Ricci

IPC分类号： G06F12/08 ,  G06F13/36

CPC分类号： G06F13/36 ,  G06F12/0831

摘要： A User bus lockout prevention mechanism for use in a time-shared busy multiple bus User, computer architecture where bus Users include private cache systems which perform a cache cycle when a WRITE TO MEMORY instruction occurs on the bus to determine if data cached from main memory has been overwritten in main memory. A User can be locked out from use of the bus if a synchronism occurs between repetative cache cycles and periodicity of the Retry mechanism of the User. Bus lockout is prevented by the User with the cache issuing an INHIBIT WRITE to the bus when a cache cycle is being performed. Other Users inhibit issuing WRITE TO MEMORY requests to the bus until the INHIBIT WRITE signal terminates. Bus requests other than a write request may be issued to the bus during INHIBIT WRITE.

摘要翻译： 用于时分多址的多总线用户总线锁定预防机制用户，计算机架构，其中总线用户包括专用缓存系统，当在总线上发生写入存储器指令以确定从主存储器缓存数据时执行缓存周期 已被主记忆所覆盖。 如果在重复高速缓存周期和用户的重试机制的周期之间发生同步，则用户可以被禁止使用总线。 当执行高速缓存循环时，用户阻止总线锁定，缓存在总线上发出INHIBIT WRITE。 其他用户禁止向总线发出WRITE TO MEMORY请求，直到INHIBIT WRITE信号终止。 在写入请求期间的总线请求可以在INHIBIT WRITE期间发送到总线。

公开(公告)号：US4613954A

公开(公告)日：1986-09-23

申请号：US756563

申请日：1985-07-18

申请人： Jayesh V. Sheth

发明人： Jayesh V. Sheth

IPC分类号： G06F3/06 ,  G06F13/12 ,  G06F13/28 ,  G06F3/00 ,  G06F13/00

CPC分类号： G06F13/124 ,  G06F13/28 ,  G06F3/06

摘要： A block counter sensing system for monitoring the occupation-status of word-blocks in a buffer memory of a peripheral-controller having Automatic Read/Write Logic for buffer-peripheral tape transfers and a burst mode routine for rapid host-buffer transfers of data words. The sensing system provides means to inform a microcode sequencer when certain action routines should be executed in order to maintain steady error-free data transfer operations which minimize the need for retries of data transfer cycles previously initiated.

摘要翻译： 一种用于监控具有用于缓冲器外围磁带传送的自动读/写逻辑的外围控制器的缓冲存储器中的字块的占用状态的块计数器感测系统，以及用于数据字的快速主机 - 缓冲器传输的突发模式例程 。 感测系统提供了在执行某些动作程序时通知微码序列器的手段，以便保持稳定的无错误数据传输操作，从而最小化先前启动的数据传输循环重试的需要。

公开(公告)号：US4542457A

公开(公告)日：1985-09-17

申请号：US457178

申请日：1983-01-11

申请人： David J. Mortensen ,  Jayesh V. Sheth

发明人： David J. Mortensen ,  Jayesh V. Sheth

IPC分类号： G06F13/10 ,  G06F3/06 ,  G06F13/12 ,  G06F13/28 ,  G06F13/38 ,  G06F9/00

CPC分类号： G06F13/28 ,  G06F13/124

摘要： A data transfer system whereby a peripheral-controller manages data transfers between the host computer and a magnetic tape peripheral unit. Data undergoing transit, is temporarily stored in a buffer memory of the peripheral-controller and is monitored by a block counter monitoring system which informs a program-sequencer in the common control circuit unit of the peripheral-controller when data may be shifted into or out of the buffer memory in order to avoid or reduce the probability of access error conditions.

摘要翻译： 一种数据传输系统，其中外围控制器管理主计算机和磁带外围单元之间的数据传输。 正在进行中转的数据被临时存储在外围控制器的缓冲存储器中，并且被块计数器监视系统监视，该数据块计数器监视系统在数据可能被移入或移出时通知外围控制器的公共控制电路单元中的程序定序器 的缓冲存储器，以避免或降低访问错误条件的概率。

公开(公告)号：US4534013A

公开(公告)日：1985-08-06

申请号：US509796

申请日：1983-06-30

申请人： Jayesh V. Sheth

发明人： Jayesh V. Sheth

IPC分类号： G06F3/06 ,  G06F13/12 ,  G06F3/00

CPC分类号： G06F3/0601 ,  G06F13/124 ,  G06F2003/0698

摘要： A peripheral-controller is used to manage data transfers between magnetic tape peripheral units and a main host computer. A program sequencer in the peripheral-controller can initiate an automatic read-write selection logic and control unit to operate in the "automatic write" mode whereby an automatic write-logic unit will transfer data out of a buffer memory in the peripheral-controller and into a magnetic tape control unit on a continuous basis without further instructions being required from the program sequencer.

摘要翻译： 外围控制器用于管理磁带外围设备和主主机之间的数据传输。 外围控制器中的程序定序器可以启动自动读写选择逻辑和控制单元以“自动写入”模式操作，由此自动写逻辑单元将数据从外围控制器中的缓冲存储器传送出去，以及 连续进入磁带控制单元，而不需要程序定序器的进一步说明。

公开(公告)号：US5511224A

公开(公告)日：1996-04-23

申请号：US406811

申请日：1995-03-16

申请人： Dan T. Tran ,  Paul B. Ricci ,  Jayesh V. Sheth ,  Theodore C. White ,  Richard A. Cowgill

发明人： Dan T. Tran ,  Paul B. Ricci ,  Jayesh V. Sheth ,  Theodore C. White ,  Richard A. Cowgill

IPC分类号： G06F11/20 ,  G06F15/173 ,  G06F11/16

CPC分类号： G06F15/173 ,  G06F11/2007 ,  G06F2201/85

摘要： A network of digital modules having store-through and non-store-through cache memories, is provided with intercommunication capability by means of two sets of system busses each of which are replicates of each other. The system busses provide a higher throughput by both being available to each of the digital modules so that a requesting digital module can alternately use a second system bus if the first system bus happens to be busy. Failure of one system bus will allocate transmission service to the second operating system bus thus providing redundancy. Alternatively, each of the system busses can be isolated for partitioning the digital modules into two different operating systems which are independent of each other.

摘要翻译： 具有存储和非存储缓存存储器的数字模块的网络通过两组系统总线被提供有相互通信能力，每组系统总线彼此是复制的。 系统总线通过两者可用于每个数字模块来提供更高的吞吐量，使得如果第一系统总线恰好忙着，请求数字模块可以交替地使用第二系统总线。 一个系统总线的故障将分配传输服务给第二个操作系统总线，从而提供冗余。 或者，可以隔离每个系统总线以将数字模块分隔成彼此独立的两个不同的操作系统。

公开(公告)号：US5349620A

公开(公告)日：1994-09-20

申请号：US003925

申请日：1993-01-12

申请人： Theodore C. White ,  Jayesh V. Sheth ,  Kha Nguyen

发明人： Theodore C. White ,  Jayesh V. Sheth ,  Kha Nguyen

IPC分类号： G04F10/00 ,  H03K21/40

CPC分类号： H03K21/40 ,  G04F10/00

摘要： An apparatus is disclosed that provides control of access to a module. In particular, the module should not be accessed while in a busy or unstable state. The module disclosed herein, by way of example, is a timer module. Access to the timer is controlled by the disclosed apparatus while the timer is changing state.

摘要翻译： 公开了提供对模块的访问的控制的装置。 特别地，在繁忙或不稳定状态时，不应该访问该模块。 作为示例，本文公开的模块是定时器模块。 当定时器正在改变状态时，由所公开的设备控制定时器的访问。

公开(公告)号：US4607348A

公开(公告)日：1986-08-19

申请号：US727603

申请日：1985-04-26

申请人： Jayesh V. Sheth

发明人： Jayesh V. Sheth

IPC分类号： G06F3/06 ,  G06F13/12

CPC分类号： G06F3/06

摘要： A data transfer system for transferring data from magnetic tape peripheral units to a peripheral-controller for temporary storage and subsequent transfer to a host computer. A tape control unit, connected to the magnetic tape peripheral units, provides clock signals to a synchronization logic circuit which controls the transfer of data through two sequential latching registers to a buffer memory in the peripheral-controller. The two sequential latching registers function as a buffering delay element together with an automatic read logic unit which allows the read logic unit to use a lesser number of cycle-steal times than would ordinarily be required, while still controlling a steady uninterrupted flow of data words.

摘要翻译： 一种用于将数据从磁带外围设备传送到外围控制器以进行临时存储并随后传送到主机的数据传输系统。 连接到磁带外围单元的磁带控制单元向同步逻辑电路提供时钟信号，同步逻辑电路通过两个顺序锁存寄存器将数据传送到外围控制器中的缓冲存储器。 两个顺序的锁存寄存器与自动读取逻辑单元一起用作缓冲延迟元件，其允许读取逻辑单元使用比通常需要的更少数量的周期窃取时间，同时仍然控制数据字的稳定的不间断的流 。

公开(公告)号：US5386517A

公开(公告)日：1995-01-31

申请号：US8962

申请日：1993-01-26

申请人： Jayesh V. Sheth ,  Craig W. Harris ,  Theodore C. White ,  Kha Nguyen ,  Chung W. Wong ,  Richard A. Cowgill

发明人： Jayesh V. Sheth ,  Craig W. Harris ,  Theodore C. White ,  Kha Nguyen ,  Chung W. Wong ,  Richard A. Cowgill

IPC分类号： G06F13/38 ,  G06F15/17 ,  G06F15/173 ,  G06F5/06

CPC分类号： G06F15/173 ,  G06F13/385 ,  G06F15/17

摘要： An Input/Output Module (IOM) interfacing multiple computers attached to a dual system bus. The IOM provides an interbus module which interfaces the dual system bus to a sub-requestor bus connecting multiple sub-requestor modules. The sub-requestor modules control a plurality of interface adaptors permitting data transfers to/from a variety of peripherals using different data protocols and clock rates. The requirements for the main host processors and memories in a computer system would be unduly burdensome were it not for the relief from these overhead operations by the input/output module which provides the tailoring of data transfer capability to and from a multiplicity of peripherals having many different types of protocols and clock rates.

摘要翻译： 输入/输出模块（IOM）连接到连接到双系统总线的多台计算机。 IOM提供了一个Interbus模块，其将双系统总线连接到连接多个子请求者模块的子请求者总线。 子请求者模块控制多个接口适配器，允许使用不同的数据协议和时钟速率向各种外设进行数据传输。 对于计算机系统中的主要主处理器和存储器的要求将是过度繁重的，这不是为了通过输入/输出模块缓解这些开销操作，其提供数据传输能力与多个具有许多外围设备的外围设备 不同类型的协议和时钟速率。

公开(公告)号：US5293621A

公开(公告)日：1994-03-08

申请号：US2566

申请日：1993-01-11

申请人： Theodore C. White ,  Jayesh V. Sheth ,  Paul B. Ricci ,  Dan T. Tran

发明人： Theodore C. White ,  Jayesh V. Sheth ,  Paul B. Ricci ,  Dan T. Tran

IPC分类号： G06F13/16 ,  G06F13/42

CPC分类号： G06F13/1689

摘要： A User bus lockout prevention mechanism for use in a time-shared bus, multiple bus User, computer architecture where bus Users have private cache systems which perform a cache cycle when a WRITE TO MEMORY instruction occurs on the bus to determine if data cached from main memory has been overwritten in main memory. A User can be locked out from use of the bus if a synchronism occurs between repetitive cache cycles and periodicity of the request Retry mechanism of the User. Bus lockout is prevented by controlling the Retry mechanism of the User to retry requests in accordance with a sequence of varying retry wait intervals. The sequence comprises bursts of short wait intervals interleaved with long wait intervals, the sequence beginning with a burst of short wait intervals. The wait interval durations of the first and second occurring bursts are interleaved with respect to each other. The second occurring long wait is longer than the first occurring long wait. The sequence is terminated upon bus grant.

摘要翻译： 一种用于时分共享总线，多总线用户，计算机架构的用户总线锁定预防机制，其中总线用户具有专用高速缓存系统，当总线上发生写入存储器指令以执行高速缓存循环，以确定是否从主站缓存数据 内存已被主内存覆盖。 如果在重复高速缓存周期与用户的请求重试机制的周期之间发生同步，则用户可以被禁止使用总线。 通过控制用户的重试机制根据不同的重试等待间隔的顺序重试请求来防止总线锁定。 该序列包括具有长等待间隔交错的短等待间隔的脉冲串，序列以短等待间隔的脉冲串开始。 第一和第二发生突发的等待间隔持续时间彼此交错。 第二次发生长时间的等待时间长于首次发生的长时间等待。 总线授予后，该序列终止。