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1.发明授权Configurable network using dual system busses with common protocol compatible for store-through and non-store-through cache memories 失效可配置的网络使用具有通用协议的双系统总线，用于存储和非存储缓存存储器
公开(公告)号：US5511224A
公开(公告)日：1996-04-23
申请号：US406811
申请日：1995-03-16
IPC分类号： G06F11/20 , G06F15/173 , G06F11/16
CPC分类号： G06F15/173 , G06F11/2007 , G06F2201/85
摘要： A network of digital modules having store-through and non-store-through cache memories, is provided with intercommunication capability by means of two sets of system busses each of which are replicates of each other. The system busses provide a higher throughput by both being available to each of the digital modules so that a requesting digital module can alternately use a second system bus if the first system bus happens to be busy. Failure of one system bus will allocate transmission service to the second operating system bus thus providing redundancy. Alternatively, each of the system busses can be isolated for partitioning the digital modules into two different operating systems which are independent of each other.
摘要翻译： 具有存储和非存储缓存存储器的数字模块的网络通过两组系统总线被提供有相互通信能力，每组系统总线彼此是复制的。 系统总线通过两者可用于每个数字模块来提供更高的吞吐量，使得如果第一系统总线恰好忙着，请求数字模块可以交替地使用第二系统总线。 一个系统总线的故障将分配传输服务给第二个操作系统总线，从而提供冗余。 或者，可以隔离每个系统总线以将数字模块分隔成彼此独立的两个不同的操作系统。
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公开(公告)号：US5293496A
公开(公告)日：1994-03-08
申请号：US3352
申请日：1993-01-12
申请人： Theodore C. White , Jayesh V. Sheth , Dan T. Tran , Paul B. Ricci
发明人： Theodore C. White , Jayesh V. Sheth , Dan T. Tran , Paul B. Ricci
CPC分类号： G06F13/36 , G06F12/0831
摘要： A User bus lockout prevention mechanism for use in a time-shared busy multiple bus User, computer architecture where bus Users include private cache systems which perform a cache cycle when a WRITE TO MEMORY instruction occurs on the bus to determine if data cached from main memory has been overwritten in main memory. A User can be locked out from use of the bus if a synchronism occurs between repetative cache cycles and periodicity of the Retry mechanism of the User. Bus lockout is prevented by the User with the cache issuing an INHIBIT WRITE to the bus when a cache cycle is being performed. Other Users inhibit issuing WRITE TO MEMORY requests to the bus until the INHIBIT WRITE signal terminates. Bus requests other than a write request may be issued to the bus during INHIBIT WRITE.
摘要翻译： 用于时分多址的多总线用户总线锁定预防机制用户，计算机架构，其中总线用户包括专用缓存系统，当在总线上发生写入存储器指令以确定从主存储器缓存数据时执行缓存周期 已被主记忆所覆盖。 如果在重复高速缓存周期和用户的重试机制的周期之间发生同步，则用户可以被禁止使用总线。 当执行高速缓存循环时，用户阻止总线锁定，缓存在总线上发出INHIBIT WRITE。 其他用户禁止向总线发出WRITE TO MEMORY请求，直到INHIBIT WRITE信号终止。 在写入请求期间的总线请求可以在INHIBIT WRITE期间发送到总线。
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3.发明授权
公开(公告)号：US5293621A
公开(公告)日：1994-03-08
申请号：US2566
申请日：1993-01-11
申请人： Theodore C. White , Jayesh V. Sheth , Paul B. Ricci , Dan T. Tran
发明人： Theodore C. White , Jayesh V. Sheth , Paul B. Ricci , Dan T. Tran
CPC分类号： G06F13/1689
摘要： A User bus lockout prevention mechanism for use in a time-shared bus, multiple bus User, computer architecture where bus Users have private cache systems which perform a cache cycle when a WRITE TO MEMORY instruction occurs on the bus to determine if data cached from main memory has been overwritten in main memory. A User can be locked out from use of the bus if a synchronism occurs between repetitive cache cycles and periodicity of the request Retry mechanism of the User. Bus lockout is prevented by controlling the Retry mechanism of the User to retry requests in accordance with a sequence of varying retry wait intervals. The sequence comprises bursts of short wait intervals interleaved with long wait intervals, the sequence beginning with a burst of short wait intervals. The wait interval durations of the first and second occurring bursts are interleaved with respect to each other. The second occurring long wait is longer than the first occurring long wait. The sequence is terminated upon bus grant.
摘要翻译： 一种用于时分共享总线，多总线用户，计算机架构的用户总线锁定预防机制，其中总线用户具有专用高速缓存系统，当总线上发生写入存储器指令以执行高速缓存循环，以确定是否从主站缓存数据 内存已被主内存覆盖。 如果在重复高速缓存周期与用户的请求重试机制的周期之间发生同步，则用户可以被禁止使用总线。 通过控制用户的重试机制根据不同的重试等待间隔的顺序重试请求来防止总线锁定。 该序列包括具有长等待间隔交错的短等待间隔的脉冲串，序列以短等待间隔的脉冲串开始。 第一和第二发生突发的等待间隔持续时间彼此交错。 第二次发生长时间的等待时间长于首次发生的长时间等待。 总线授予后，该序列终止。
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公开(公告)号：US5349620A
公开(公告)日：1994-09-20
申请号：US003925
申请日：1993-01-12
申请人： Theodore C. White , Jayesh V. Sheth , Kha Nguyen
发明人： Theodore C. White , Jayesh V. Sheth , Kha Nguyen
摘要： An apparatus is disclosed that provides control of access to a module. In particular, the module should not be accessed while in a busy or unstable state. The module disclosed herein, by way of example, is a timer module. Access to the timer is controlled by the disclosed apparatus while the timer is changing state.
摘要翻译： 公开了提供对模块的访问的控制的装置。 特别地，在繁忙或不稳定状态时，不应该访问该模块。 作为示例，本文公开的模块是定时器模块。 当定时器正在改变状态时，由所公开的设备控制定时器的访问。
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公开(公告)号：US5519883A
公开(公告)日：1996-05-21
申请号：US18829
申请日：1993-02-18
CPC分类号： G06F11/2007 , G06F13/4027
摘要： An interbus interface module enables storage and transfer of commands, messages and data between parallel a dual system bus operating on a first protocol and a subrequestor bus operating on a second protocol. The interface module serves a first group of requestors, such as multiple processors and main memory, for handling data transfers to and from the subrequestor bus via said dual system buses while also handling data transfers to and from a second group of requestors connected to the subrequestor bus.
摘要翻译： Interbus接口模块能够在并行运行在第一协议上的双系统总线和在第二协议上工作的子请求总线之间存储和传送命令，消息和数据。 接口模块服务第一组请求者，例如多处理器和主存储器，用于经由所述双系统总线处理到和从子请求总线的数据传输，同时还处理到和连接到子请求器的第二组请求者的数据传输 总线。
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6.发明授权Dual bus communication system connecting multiple processors to multiple I/O subsystems having a plurality of I/O devices with varying transfer speeds 失效将多个处理器连接到具有变化的传送速度的多个I / O设备的多个I / O子系统的双总线通信系统
公开(公告)号：US5386517A
公开(公告)日：1995-01-31
申请号：US8962
申请日：1993-01-26
申请人： Jayesh V. Sheth , Craig W. Harris , Theodore C. White , Kha Nguyen , Chung W. Wong , Richard A. Cowgill
发明人： Jayesh V. Sheth , Craig W. Harris , Theodore C. White , Kha Nguyen , Chung W. Wong , Richard A. Cowgill
IPC分类号： G06F13/38 , G06F15/17 , G06F15/173 , G06F5/06
CPC分类号： G06F15/173 , G06F13/385 , G06F15/17
摘要： An Input/Output Module (IOM) interfacing multiple computers attached to a dual system bus. The IOM provides an interbus module which interfaces the dual system bus to a sub-requestor bus connecting multiple sub-requestor modules. The sub-requestor modules control a plurality of interface adaptors permitting data transfers to/from a variety of peripherals using different data protocols and clock rates. The requirements for the main host processors and memories in a computer system would be unduly burdensome were it not for the relief from these overhead operations by the input/output module which provides the tailoring of data transfer capability to and from a multiplicity of peripherals having many different types of protocols and clock rates.
摘要翻译： 输入/输出模块（IOM）连接到连接到双系统总线的多台计算机。 IOM提供了一个Interbus模块，其将双系统总线连接到连接多个子请求者模块的子请求者总线。 子请求者模块控制多个接口适配器，允许使用不同的数据协议和时钟速率向各种外设进行数据传输。 对于计算机系统中的主要主处理器和存储器的要求将是过度繁重的，这不是为了通过输入/输出模块缓解这些开销操作，其提供数据传输能力与多个具有许多外围设备的外围设备 不同类型的协议和时钟速率。
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公开(公告)号：US07287102B1
公开(公告)日：2007-10-23
申请号：US10761786
申请日：2004-01-21
CPC分类号： G06F3/0656 , G06F3/0608 , G06F3/0638 , G06F3/0682
摘要： A storage controller includes a first memory that stores a plurality of data blocks that include first and second noncontiguous data segments. A queue module stores data lengths and data start addresses of the first and second data segments. A read assembly module communicates with the first memory and the queue module, receives a request to read the first and second data segments from a host, reads the plurality of data blocks from the first memory, extracts the first and second data segments from the read plurality of data blocks based on the data lengths and data start addresses after the plurality of data blocks is read from the first memory, and transfers the first and second data segments contiguously to the host.
摘要翻译： 存储控制器包括存储包括第一和第二非连续数据段的多个数据块的第一存储器。 队列模块存储第一和第二数据段的数据长度和数据开始地址。 读取组件模块与第一存储器和队列模块通信，接收从主机读取第一和第二数据段的请求，从第一存储器读取多个数据块，从读取中提取第一和第二数据段 基于从第一存储器读取多个数据块之后的数据长度和数据开始地址的多个数据块，并将第一和第二数据段连续地传送到主机。
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公开(公告)号：US08095717B1
公开(公告)日：2012-01-10
申请号：US12250895
申请日：2008-10-14
申请人： Theodore C. White
发明人： Theodore C. White
CPC分类号： G06F3/0619 , G06F3/0656 , G06F3/0658 , G06F3/0676 , H04L7/00 , H04L7/0012 , H04L7/0045
摘要： A system includes a data holding module that at least one of stores and receives data based on a first clock signal of a first clock domain. A data output module receives the data from the data holding module and selectively outputs the data based on a load signal and a second clock signal of a second clock domain which is asynchronous to the first clock domain. A synchronization process module generates the load signal based on a state of the data output module.
摘要翻译： 一种系统包括：数据保持模块，其基于第一时钟域的第一时钟信号存储和接收数据中的至少一个。 数据输出模块从数据保持模块接收数据，并且基于与第一时钟域异步的第二时钟域的负载信号和第二时钟信号有选择地输出数据。 同步处理模块基于数据输出模块的状态生成负载信号。
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公开(公告)号：US07535791B1
公开(公告)日：2009-05-19
申请号：US11977169
申请日：2007-10-23
IPC分类号： G11C8/00
CPC分类号： G06F13/1689
摘要： A memory system includes Synchronous Dynamic Random Access Memory (SDRAM) A memory controller communicates with the memory, generates an SDRAM clock signal, that receives a bi-directional sampling clock signal (DQS) that is generated based on the SDRAM clock signal, and reads data from the memory based on the DQS.
摘要翻译： 存储器系统包括同步动态随机存取存储器（SDRAM）。 存储器控制器与存储器通信，产生SDRAM时钟信号，其接收基于SDRAM时钟信号生成的双向采样时钟信号（DQS），并且基于DQS从存储器读取数据。
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公开(公告)号：US08713224B2
公开(公告)日：2014-04-29
申请号：US11232437
申请日：2005-09-21
IPC分类号： G06F13/10
CPC分类号： G06F13/28 , G06F13/1673 , G06F13/1678
摘要： A method and system for processing data by a storage controller with a buffer controller coupled to a buffer memory is provided. The method includes, evaluating incoming data block size; determining if the incoming data requires padding; and padding incoming data such that the incoming data can be processed by the buffer controller. The method also includes determining if any pads need to be removed from data that is read from the buffer memory; and removing pads from the data read from the buffer memory. The buffer controller can be set in a mode to receive any MOD size data and includes a first channel with a FIFO for receiving incoming data via a first interface. The buffer controller mode for receiving incoming data can be set by firmware.
摘要翻译： 提供了一种由具有耦合到缓冲存储器的缓冲器控制器的存储控制器处理数据的方法和系统。 该方法包括：评估输入数据块大小; 确定输入数据是否需要填充; 并填充传入数据，使得输入数据可以由缓冲器控制器处理。 该方法还包括确定是否需要从从缓冲存储器读取的数据中去除任何焊盘; 以及从缓冲存储器读取的数据中移除焊盘。 可以将缓冲器控制器设置为接收任何MOD尺寸数据的模式，并且包括具有FIFO的第一通道，用于经由第一接口接收输入数据。 用于接收传入数据的缓冲控制器模式可以通过固件来设置。
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