公开(公告)号：US5293621A

公开(公告)日：1994-03-08

申请号：US2566

申请日：1993-01-11

申请人： Theodore C. White ,  Jayesh V. Sheth ,  Paul B. Ricci ,  Dan T. Tran

发明人： Theodore C. White ,  Jayesh V. Sheth ,  Paul B. Ricci ,  Dan T. Tran

IPC分类号： G06F13/16 ,  G06F13/42

CPC分类号： G06F13/1689

摘要： A User bus lockout prevention mechanism for use in a time-shared bus, multiple bus User, computer architecture where bus Users have private cache systems which perform a cache cycle when a WRITE TO MEMORY instruction occurs on the bus to determine if data cached from main memory has been overwritten in main memory. A User can be locked out from use of the bus if a synchronism occurs between repetitive cache cycles and periodicity of the request Retry mechanism of the User. Bus lockout is prevented by controlling the Retry mechanism of the User to retry requests in accordance with a sequence of varying retry wait intervals. The sequence comprises bursts of short wait intervals interleaved with long wait intervals, the sequence beginning with a burst of short wait intervals. The wait interval durations of the first and second occurring bursts are interleaved with respect to each other. The second occurring long wait is longer than the first occurring long wait. The sequence is terminated upon bus grant.

摘要翻译： 一种用于时分共享总线，多总线用户，计算机架构的用户总线锁定预防机制，其中总线用户具有专用高速缓存系统，当总线上发生写入存储器指令以执行高速缓存循环，以确定是否从主站缓存数据 内存已被主内存覆盖。 如果在重复高速缓存周期与用户的请求重试机制的周期之间发生同步，则用户可以被禁止使用总线。 通过控制用户的重试机制根据不同的重试等待间隔的顺序重试请求来防止总线锁定。 该序列包括具有长等待间隔交错的短等待间隔的脉冲串，序列以短等待间隔的脉冲串开始。 第一和第二发生突发的等待间隔持续时间彼此交错。 第二次发生长时间的等待时间长于首次发生的长时间等待。 总线授予后，该序列终止。

公开(公告)号：US5293496A

公开(公告)日：1994-03-08

申请号：US3352

申请日：1993-01-12

申请人： Theodore C. White ,  Jayesh V. Sheth ,  Dan T. Tran ,  Paul B. Ricci

发明人： Theodore C. White ,  Jayesh V. Sheth ,  Dan T. Tran ,  Paul B. Ricci

IPC分类号： G06F12/08 ,  G06F13/36

CPC分类号： G06F13/36 ,  G06F12/0831

摘要： A User bus lockout prevention mechanism for use in a time-shared busy multiple bus User, computer architecture where bus Users include private cache systems which perform a cache cycle when a WRITE TO MEMORY instruction occurs on the bus to determine if data cached from main memory has been overwritten in main memory. A User can be locked out from use of the bus if a synchronism occurs between repetative cache cycles and periodicity of the Retry mechanism of the User. Bus lockout is prevented by the User with the cache issuing an INHIBIT WRITE to the bus when a cache cycle is being performed. Other Users inhibit issuing WRITE TO MEMORY requests to the bus until the INHIBIT WRITE signal terminates. Bus requests other than a write request may be issued to the bus during INHIBIT WRITE.

摘要翻译： 用于时分多址的多总线用户总线锁定预防机制用户，计算机架构，其中总线用户包括专用缓存系统，当在总线上发生写入存储器指令以确定从主存储器缓存数据时执行缓存周期 已被主记忆所覆盖。 如果在重复高速缓存周期和用户的重试机制的周期之间发生同步，则用户可以被禁止使用总线。 当执行高速缓存循环时，用户阻止总线锁定，缓存在总线上发出INHIBIT WRITE。 其他用户禁止向总线发出WRITE TO MEMORY请求，直到INHIBIT WRITE信号终止。 在写入请求期间的总线请求可以在INHIBIT WRITE期间发送到总线。

公开(公告)号：US5511224A

公开(公告)日：1996-04-23

申请号：US406811

申请日：1995-03-16

申请人： Dan T. Tran ,  Paul B. Ricci ,  Jayesh V. Sheth ,  Theodore C. White ,  Richard A. Cowgill

发明人： Dan T. Tran ,  Paul B. Ricci ,  Jayesh V. Sheth ,  Theodore C. White ,  Richard A. Cowgill

IPC分类号： G06F11/20 ,  G06F15/173 ,  G06F11/16

CPC分类号： G06F15/173 ,  G06F11/2007 ,  G06F2201/85

摘要： A network of digital modules having store-through and non-store-through cache memories, is provided with intercommunication capability by means of two sets of system busses each of which are replicates of each other. The system busses provide a higher throughput by both being available to each of the digital modules so that a requesting digital module can alternately use a second system bus if the first system bus happens to be busy. Failure of one system bus will allocate transmission service to the second operating system bus thus providing redundancy. Alternatively, each of the system busses can be isolated for partitioning the digital modules into two different operating systems which are independent of each other.

摘要翻译： 具有存储和非存储缓存存储器的数字模块的网络通过两组系统总线被提供有相互通信能力，每组系统总线彼此是复制的。 系统总线通过两者可用于每个数字模块来提供更高的吞吐量，使得如果第一系统总线恰好忙着，请求数字模块可以交替地使用第二系统总线。 一个系统总线的故障将分配传输服务给第二个操作系统总线，从而提供冗余。 或者，可以隔离每个系统总线以将数字模块分隔成彼此独立的两个不同的操作系统。

公开(公告)号：US5495573A

公开(公告)日：1996-02-27

申请号：US286855

申请日：1994-08-05

申请人： Wayne C. Datwyler ,  Long V. Ha ,  Dan T. Tran

发明人： Wayne C. Datwyler ,  Long V. Ha ,  Dan T. Tran

IPC分类号： G06F11/07 ,  G11C29/00

CPC分类号： G06F11/0772 ,  G06F11/0745

摘要： An error logging system where errors are captured on dual system busses operating at a lower clock rate (16 MHz) than the processor which receives the error information. The system functions to substantially reduce the loads on the processor in addition to maximizing the use of the system bus drivers which are pin-constrained. The processor operates at a higher clock rate (32 MHz). Processor commands to read error data from an error log register are synchronized down to the 16 MHz rate, then enabled onto a processor bus after a second synchronization operation back to the higher (32 MHz) rate. Provision is made for identifying several different types of error categories. An expandable error log register system is provided which uses selected bit positions to identify types of errors logged to the processor which also enables expansitivity for adding in future types of errors into the error logging system and renders compatibility for a processor operating at first clock rate with error data sensed at a second clock rate.

摘要翻译： 错误记录系统，其错误捕获在以比接收错误信息的处理器更低的时钟速率（16MHz）工作的双系统总线上。 除了最大限度地利用被引脚约束的系统总线驱动器之外，该系统还用于大大减少处理器上的负载。 处理器工作在更高的时钟频率（32 MHz）。 从错误日志寄存器读取错误数据的处理器命令被同步到16 MHz速率，然后在第二个同步操作回到较高（32 MHz）速率之后启用到处理器总线上。 提供了确定几种不同类型的错误类别。 提供了一种可扩展的错误日志寄存器系统，其使用所选择的位位置来识别记录到处理器的错误类型，该错误日志寄存器系统还能够扩展以将未来类型的错误添加到错误记录系统中，并且使得以第一时钟速率操作的处理器的兼容性与 以第二时钟速率感测的误差数据。

公开(公告)号：US5553249A

公开(公告)日：1996-09-03

申请号：US400700

申请日：1995-03-08

申请人： Wayne C. Datwyler ,  Dan T. Tran ,  Long V. Ha

发明人： Wayne C. Datwyler ,  Dan T. Tran ,  Long V. Ha

IPC分类号： G06F12/08 ,  G06F13/40 ,  G06F13/42

CPC分类号： G06F13/4013 ,  G06F13/4018 ,  G06F12/0804

摘要： A single chip data path gate array interface links a central processing unit, operating at a first clock rate and single word protocol, to dual system busses operating at a second clock rate and multiple-word protocol. The data path interface holds command, data and message registers, controlled by external logic, in an input channel pathway and an output channel pathway. The interface chip is basically limited to registers and multiplexers making it flexible for use in different architectures such as both Store-Through and Non-Store-Through cache protocols. In addition, such a simplified chip is simple to fabricate and to maintain free of defects.

摘要翻译： 单芯片数据路径门阵列接口将以第一时钟速率和单字协议操作的中央处理单元链接到以第二时钟速率和多字协议操作的双系统总线。 数据路径接口保持由外部逻辑控制的命令，数据和消息寄存器，在输入通道路径和输出通道路径中。 接口芯片基本上限于寄存器和多路复用器，使其灵活地用于不同架构，如存储直通和非存储缓存协议。 此外，这种简化的芯片制造简单，并且没有缺陷。

公开(公告)号：US5444722A

公开(公告)日：1995-08-22

申请号：US18949

申请日：1993-02-17

申请人： Dan T. Tran

发明人： Dan T. Tran

IPC分类号： G11C29/00 ,  G11C29/02 ,  H04Q11/04

CPC分类号： G11C29/88 ,  G11C29/02

摘要： A memory module is used in multiples on a bus in a data processing system. Each memory module comprises a plurality of storage cells, an input circuit for receiving a read command and a read address from the bus, and a compare circuit which generates a match signal when the read address is within a selectable address range for the storage cells. Also, the module further includes: a control circuit, coupled to the compare circuit, which responds to the match signal by almost always executing the read command in a small time interval on the bus and occasionally executing the read command in a long time interval. Further, the module includes a bus transmit circuit, coupled to the control circuit, for sending a control signal on the bus if the control circuit selects the long time interval. Also, the module includes an error circuit, coupled to the control circuit and the bus, for setting an error flag if the control circuit selects the short time interval and, during that short time interval, the control signal is detected on the bus from another module in the memory system.

摘要翻译： 存储器模块在数据处理系统中的总线上被多次使用。 每个存储器模块包括多个存储单元，用于从总线接收读取命令和读取地址的输入电路，以及当读取地址在存储单元的可选地址范围内时产生匹配信号的比较电路。 此外，模块还包括：耦合到比较电路的控制电路，其通过总线上几乎总是执行读取命令的时间间隔来响应匹配信号，并且偶尔以长时间间隔执行读取命令。 此外，如果控制电路选择长时间间隔，则模块包括耦合到控制电路的总线发送电路，用于在总线上发送控制信号。 此外，模块包括耦合到控制电路和总线的误差电路，用于设置错误标志，如果控制电路选择短时间间隔，并且在该短时间间隔期间，在总线上从另一个检测到控制信号 模块在内存系统中。

公开(公告)号：US5598421A

公开(公告)日：1997-01-28

申请号：US390712

申请日：1995-02-17

申请人： Dan T. Tran ,  Wayne C. Datwyler ,  Long V. Ha

发明人： Dan T. Tran ,  Wayne C. Datwyler ,  Long V. Ha

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318536

摘要： The logic circuitry of an IC chip is connected to JTAG register chains which hold state information on each portion of the logic circuitry therein. A JTAG Tracker Module is connected to the controls of each of the JTAG register chains enabling a programmer-operator to read the present state of each JTAG register chain and enabling a readout of the logic circuits condition in a single clock period.

摘要翻译： IC芯片的逻辑电路连接到JTAG寄存器链，其保持逻辑电路的每个部分上的状态信息。 JTAG跟踪器模块连接到每个JTAG寄存器链的控制，使得编程器操作者可以读取每个JTAG寄存器链的当前状态，并且可以在单个时钟周期内读出逻辑电路条件。