公开(公告)号：US06281109B1

公开(公告)日：2001-08-28

申请号：US09571074

申请日：2000-05-15

Applicant: Manny Ma ,  Trung Doan ,  Jeff Zhiqiang Wu

Inventor： Manny Ma ,  Trung Doan ,  Jeff Zhiqiang Wu

IPC: H01L214763

CPC classification number: H01L21/76838 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An exemplary implementation of the present invention includes a method for forming conductive lines fabricated in a semiconductor device, the method comprising the steps of forming a first layer of patterned conductive lines, having substantially vertical sidewalls, on a supporting material; of forming insulative spacers about the substantially vertical sidewalls; of forming trenches into the supporting material that align to the insulative spacers; and of forming a second layer of patterned conductive lines such that each line is at least partially embedded within a corresponding trench. Preferably, the conductive lines, formed by a double metal process, are recessed into a supporting material that has a substantially planar surface.

Abstract translation: 本发明的示例性实施方案包括一种用于形成在半导体器件中制造导电线的方法，该方法包括以下步骤：在支撑材料上形成具有基本上垂直的侧壁的图案化导电线的第一层; 围绕所述基本上垂直的侧壁形成绝缘隔离物; 将沟槽形成到与绝缘间隔件对准的支撑材料中; 并且形成图案化导电线的第二层，使得每条线至少部分地嵌入相应的沟槽内。 优选地，由双金属工艺形成的导线凹入到具有基本上平坦的表面的支撑材料中。

公开(公告)号：US06184539B2

公开(公告)日：2001-02-06

申请号：US09073074

申请日：1998-05-04

Applicant: Jeff Zhiqiang Wu ,  Joseph Karniewicz

Inventor： Jeff Zhiqiang Wu ,  Joseph Karniewicz

IPC: H01L2906

CPC classification number: B82Y10/00 ,  G11C11/36 ,  G11C11/412 ,  G11C11/5621 ,  H01L27/11 ,  H01L29/7393 ,  Y10S257/903

Abstract: A static memory cell having no more than three transistors. A static memory cell comprises a semiconductor substrate of a first conductivity type; a buried layer in the substrate, the buried layer having a second conductivity type opposite to the first conductivity type; a transistor formed over the buried layer, the transistor having a source of the second conductivity type, a gate, and a drain of the second conductivity type, the source having a depth in the substrate greater than the depth of the drain; and alternating layers of insulative and conductive material formed proximate the source, including two conductive layers and two insulative layers, one of the insulative layers being in junction relation to the source.

Abstract translation: 具有不超过三个晶体管的静态存储单元。 静态存储单元包括第一导电类型的半导体衬底; 所述掩埋层在所述衬底中，所述掩埋层具有与所述第一导电类型相反的第二导电类型; 形成在所述掩埋层上的晶体管，所述晶体管具有所述第二导电类型的源极，所述第二导电类型的栅极和漏极，所述源极在所述衬底中的深度大于所述漏极的深度; 以及在源极附近形成的绝缘和导电材料的交替层，包括两个导电层和两个绝缘层，绝缘层中的一个与源极连接。

公开(公告)号：US6022783A

公开(公告)日：2000-02-08

申请号：US902763

申请日：1997-07-30

Applicant: Jeff Zhiqiang Wu

Inventor： Jeff Zhiqiang Wu

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/76

CPC classification number: H01L29/66636 ,  H01L29/7834

Abstract: A semiconductor processing method of forming an NMOS field effect transistor includes, a) providing a projecting mesa of semiconductive material from a bulk semiconductor substrate, the mesa defining a semiconductor substrate floor and walls rising upwardly therefrom; b) providing a gate dielectric layer and a gate atop the semiconductive mesa; c) providing a pair of opposing LDD regions within the semiconductive mesa, the respective LDD regions running along one of the mesa walls; and d) providing source and drain diffusion regions within the bulk semiconductor substrate floor which respectively interconnect with the opposing LDD regions of the mesa. NMOS field effect transistors are also disclosed.

Abstract translation: 形成NMOS场效应晶体管的半导体处理方法包括：a）从体半导体衬底提供半导体材料的突出台面，所述台面限定半导体衬底地板和从其向上升起的壁; b）在半导体台面的顶部提供栅极电介质层和栅极; c）在半导体台面内提供一对相对的LDD区域，各个LDD区域沿着台面壁之一延伸; 以及d）在所述体半导体衬底底板内提供分别与所述台面的相对的LDD区域互连的源极和漏极扩散区域。 还公开了NMOS场效应晶体管。

公开(公告)号：US6063673A

公开(公告)日：2000-05-16

申请号：US144512

申请日：1998-08-31

Applicant: David Y. Kao ,  Jeff Zhiqiang Wu

Inventor： David Y. Kao ,  Jeff Zhiqiang Wu

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/7835

Abstract: In one aspect, a method for forming a transistor device on a semiconductor substrate, comprising: a) forming a transistor gate on the substrate; b) forming a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; and c) forming a second polarity internal junction region, the second polarity internal junction region being entirely received within one of the first polarity regions. In another aspect, a transistor device, comprising: a) a transistor gate on a semiconductor substrate; b) a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; and c) a second polarity internal junction region entirely received within one of the first polarity regions. In yet another aspect, the invention includes a resistor, comprising: a) a gate on a semiconductor substrate, the gate being electrically powered with a gate voltage; b) a first polarity source active region and a first polarity drain active region operatively adjacent the electrically powered gate; c) a second polarity internal junction region entirely received within one of the first polarity regions; and d) a current between the first polarity source active region and the first polarity drain active region, the current being substantially linearly dependent on a voltage at the drain region.

Abstract translation: 一方面，一种在半导体衬底上形成晶体管器件的方法，包括：a）在衬底上形成晶体管栅极; b）形成与晶体管栅极可操作地相邻的第一极性源极有源区和第一极性漏极有源区; 以及c）形成第二极性内部结合区域，所述第二极性内部结合区域完全接收在所述第一极性区域之一内。 在另一方面，一种晶体管器件，包括：a）半导体衬底上的晶体管栅极; b）可操作地邻近晶体管栅极的第一极性源极有源区和第一极性漏极有源区; 以及c）完全接收在所述第一极性区域之一内的第二极性内部连接区域。 在另一方面，本发明包括一种电阻器，包括：a）半导体衬底上的栅极，栅极由栅极电压供电; b）第一极性源有源区和可操作地邻近电动门的第一极性漏极有源区; c）完全接收在所述第一极性区域之一内的第二极性内部连接区域; 以及d）所述第一极性源极活性区域和所述第一极性漏极有源区域之间的电流，所述电流基本上线性地取决于所述漏极区域处的电压。

公开(公告)号：US5672536A

公开(公告)日：1997-09-30

申请号：US657300

申请日：1996-06-03

Applicant: Jeff Zhiqiang Wu ,  Joseph Karniewicz

Inventor： Jeff Zhiqiang Wu ,  Joseph Karniewicz

IPC: H01L21/8244 ,  H01L21/8246 ,  H01L27/11 ,  H01L21/70 ,  H01L27/00

CPC classification number: H01L27/11266 ,  H01L27/11 ,  Y10S257/903 ,  Y10S257/904 ,  Y10S438/979

Abstract: A static memory cell having no more than three transistors. A static memory cell is formed by providing a semiconductor substrate; forming a buried n-type layer in the substrate, the n-type layer having a first average n-type dopant concentration of at least 1.times.10.sup.16 ions/cm.sup.3 ; forming an n-channel transistor relative to the substrate over the buried n-type layer, the n-channel transistor having a source, a gate, and a drain, the source having a second average n-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3 and the drain having a third average n-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3, and the source having a depth deeper than the drain so as to be closer to the buried n-type layer than the drain; and forming a p-type region in junction with the source to define a tunnel diode between the p-type region and the source.

Abstract translation: 具有不超过三个晶体管的静态存储单元。 通过提供半导体衬底形成静态存储单元; 在衬底中形成掩埋的n型层，n型层具有至少1×10 16个离子/ cm 3的第一平均n型掺杂剂浓度; 在所述掩埋的n型层上形成相对于所述衬底的n沟道晶体管，所述n沟道晶体管具有源极，栅极和漏极，所述源极具有至少1×1019个离子的第二平均n型掺杂剂浓度 并且所述漏极具有至少1×1019个离子/ cm 3的第三平均n型掺杂剂浓度，并且所述源的深度比所述漏极深，以便比所述漏极更接近所述掩埋的n型层; 以及在与源极连接处形成p型区域以在p型区域和源极之间限定隧道二极管。

公开(公告)号：US06404018B1

公开(公告)日：2002-06-11

申请号：US09564413

申请日：2000-05-02

Applicant: Jeff Zhiqiang Wu ,  Joseph Karniewicz

Inventor： Jeff Zhiqiang Wu ,  Joseph Karniewicz

IPC: H01L2976

CPC classification number: H01L27/11266 ,  H01L27/11 ,  Y10S257/903 ,  Y10S257/904 ,  Y10S438/979

Abstract: A static memory cell having no more than three transistors. A static memory cell is formed by providing a semiconductor substrate; forming a buried n-type layer in the substrate, the n-type layer having a first average n-type dopant concentration of at least 1×1016 ions/cm3; forming an n-channel transistor relative to the substrate over the buried n-type layer, the n-channel transistor having a source, a gate, and a drain, the source having a second average n-type dopant concentration of at least 1×1019 ions/cm3 and the drain having a third average n-type dopant concentration of at least 1×1019 ions/cm3, and the source having a depth deeper than the drain so as to be closer to the buried n-type layer than the drain; and forming a p-type region in junction with the source to define a tunnel diode between the p-type region and the source.

Abstract translation: 具有不超过三个晶体管的静态存储单元。 通过提供半导体衬底形成静态存储单元; 在衬底中形成掩埋的n型层，n型层具有至少1×10 16个离子/ cm 3的第一平均n型掺杂剂浓度; 在所述掩埋的n型层上形成相对于所述衬底的n沟道晶体管，所述n沟道晶体管具有源极，栅极和漏极，所述源极具有至少1×1019个离子的第二平均n型掺杂剂浓度 并且所述漏极具有至少1×1019个离子/ cm 3的第三平均n型掺杂剂浓度，并且所述源的深度比所述漏极深，以便比所述漏极更接近所述掩埋的n型层; 以及在与源极连接处形成p型区域以在p型区域和源极之间限定隧道二极管。

公开(公告)号：US06309935B1

公开(公告)日：2001-10-30

申请号：US09089841

申请日：1998-06-03

Applicant: Jeff Zhiqiang Wu ,  Sittampalam Yoganathan

Inventor： Jeff Zhiqiang Wu ,  Sittampalam Yoganathan

IPC: H01L218236

CPC classification number: H01L29/66575 ,  H01L21/2257 ,  H01L21/28123 ,  H01L21/823814 ,  H01L29/41783 ,  Y10S148/082 ,  Y10S148/141

Abstract: Methods of forming field effect transistors. In one aspect, a method of forming a field effect transistor includes: a) providing a gate structure over a semiconductor substrate, the gate structure comprising a conductively-doped polysilicon region and a dopant masking cap over the conductively-doped polysilicon region; b) providing a layer of polysilicon over the substrate and over the dopant masking cap of the gate structure, the polysilicon layer defining a pair of polysilicon outward projections extending from the semiconductor substrate adjacent the gate structure; c) removing the layer of polysilicon from over the dopant masking cap; d) while the dopant masking cap is over the polysilicon region, conductively doping the pair of polysilicon projections with one of an n-type or a p-type conductivity enhancing dopant impurity; and e) out-diffusing the one of the n-type conductivity enhancing dopant impurity or the p-type conductivity enhancing dopant impurity from the pair of polysilicon projections into the semiconductor substrate to provide one of NMOS or PMOS type diffusion regions, respectively, within the substrate adjacent the gate line.

Abstract translation: 形成场效应晶体管的方法。 一方面，一种形成场效应晶体管的方法包括：a）在半导体衬底上提供栅极结构，所述栅极结构包括在所述导电掺杂多晶硅区域上的导电掺杂多晶硅区域和掺杂剂掩蔽帽; b）在所述衬底上以及所述栅极结构的所述掺杂剂掩蔽盖上方提供多晶硅层，所述多晶硅层限定从所述半导体衬底相邻所述栅极结构延伸的一对多晶硅向外突出; c）从掺杂剂掩蔽盖上方去除多晶硅层; d）当掺杂剂掩蔽帽在多晶硅区域上方时，用n型或p型导电性增强掺杂剂杂质中的一种导电地掺杂该对多晶硅突起; 以及e）将所述n型导电性增强掺杂剂杂质或所述p型导电性增强掺杂剂杂质中的一种从所述一对多晶硅突起散出扩散到所述半导体衬底中，以分别在所述半导体衬底内提供NMOS或PMOS型扩散区域中的一个 衬底相邻栅极线。

公开(公告)号：US5955760A

公开(公告)日：1999-09-21

申请号：US858861

申请日：1997-05-19

Applicant: David Y. Kao ,  Jeff Zhiqiang Wu

Inventor： David Y. Kao ,  Jeff Zhiqiang Wu

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L29/6659 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/7835

Abstract: In one aspect, a method for forming a transistor device on a semiconductor substrate, comprising: a) forming a transistor gate on the substrate; b) forming a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; and c) forming a second polarity internal junction region, the second polarity internal junction region being entirely received within one of the first polarity regions. In another aspect, a transistor device, comprising: a) a transistor gate on a semiconductor substrate; b) a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; and c) a second polarity internal junction region entirely received within one of the first polarity regions. In yet another aspect, the invention includes a resistor, comprising: a) a gate on a semiconductor substrate, the gate being electrically powered with a gate voltage; b) a first polarity source active region and a first polarity drain active region operatively adjacent the electrically powered gate; c) a second polarity internal junction region entirely received within one of the first polarity regions; and d) a current between the first polarity source active region and the first polarity drain active region, the current being substantially linearly dependent on a voltage at the drain region.

Abstract translation: 一方面，一种在半导体衬底上形成晶体管器件的方法，包括：a）在衬底上形成晶体管栅极; b）形成与晶体管栅极可操作地相邻的第一极性源极有源区和第一极性漏极有源区; 以及c）形成第二极性内部结合区域，所述第二极性内部结合区域完全接收在所述第一极性区域之一内。 在另一方面，一种晶体管器件，包括：a）半导体衬底上的晶体管栅极; b）可操作地邻近晶体管栅极的第一极性源极有源区和第一极性漏极有源区; 以及c）完全接收在所述第一极性区域之一内的第二极性内部连接区域。 在另一方面，本发明包括一种电阻器，包括：a）半导体衬底上的栅极，栅极由栅极电压供电; b）第一极性源有源区和可操作地邻近电动门的第一极性漏极有源区; c）完全接收在所述第一极性区域之一内的第二极性内部连接区域; 以及d）所述第一极性源极活性区域和所述第一极性漏极有源区域之间的电流，所述电流基本上线性地取决于所述漏极区域处的电压。

公开(公告)号：US5897357A

公开(公告)日：1999-04-27

申请号：US717014

申请日：1996-09-20

Applicant: Jeff Zhiqiang Wu ,  Sittampalam Yoganathan

Inventor： Jeff Zhiqiang Wu ,  Sittampalam Yoganathan

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/66575 ,  H01L21/2257 ,  H01L21/28123 ,  H01L21/823814 ,  H01L29/41783 ,  Y10S148/082 ,  Y10S148/141

Abstract: A method of forming CMOS integrated circuitry includes, a) providing a series of field oxide regions and a series of gate lines over a semiconductor substrate, a first gate line being positioned for formation of an NMOS transistor, a second gate line being positioned for formation of a PMOS transistor; b) providing a layer of polysilicon to define a first and second pairs of polysilicon outward projections extending from the semiconductor substrate adjacent the first and second gate lines, respectively; c) masking one of the first or second pair of polysilicon projections while conductively doping the other of the first or second pair with an n-type or a p-type conductivity enhancing dopant impurity, respectively; d) masking the other of the first or second pair of polysilicon projections while conductively doping the one of the first or second pair of polysilicon projections with an n-type or a p-type conductivity enhancing dopant impurity, respectively; e) out-diffusing conductivity enhancing dopant impurity from the respective pairs of polysilicon projections into the semiconductor substrate to provide respective NMOS and PMOS type diffusion regions within the substrate adjacent the respective first and second gate lines. A combination of blanket doping and masked doping to produce the respective NMOS and PMOS type diffusion regions is also contemplated. The invention also has utility to formation of only one of NMOS or PMOS type field effect transistors, as opposed to CMOS formation.

Abstract translation: 一种形成CMOS集成电路的方法包括：a）在半导体衬底上提供一系列场氧化物区域和一系列栅极线，第一栅极线被定位用于形成NMOS晶体管，第二栅极线被定位成形成 的PMOS晶体管; b）提供多晶硅层以分别限定从所述半导体衬底相邻的所述第一和第二栅极线延伸的第一和第二对多晶硅向外突出; c）掩蔽所述第一或第二对多晶硅突起中的一个，同时分别用n型或p型导电性增强掺杂剂杂质导电地掺杂所述第一对或第二对中的另一对; d）掩蔽第一或第二对多晶硅突起中的另一个，同时分别用n型或p型导电性增强掺杂剂杂质导电地掺杂第一或第二对多晶硅突起中的一个; e）从导电半导体衬底的各对多晶硅投影对中扩散导电性增强掺杂剂杂质，以在邻近相应的第一和第二栅极线的衬底内提供相应的NMOS和PMOS型扩散区。 还考虑了覆盖掺杂和掩模掺杂以产生相应的NMOS和PMOS型扩散区域的组合。 与CMOS形成相反，本发明也可用于仅形成NMOS或PMOS型场效应晶体管中的一种。

公开(公告)号：US5811338A

公开(公告)日：1998-09-22

申请号：US694601

申请日：1996-08-09

Applicant: David Y. Kao ,  Jeff Zhiqiang Wu

Inventor： David Y. Kao ,  Jeff Zhiqiang Wu

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/7835

Abstract: In one aspect, a method for forming a transistor device on a semiconductor substrate, comprising: a) forming a transistor gate on the. substrate; b) forming a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; and c) forming a second polarity internal junction region, the second polarity internal junction region being entirely received within one of the first polarity regions. In another aspect, a transistor device, comprising: a) a transistor gate on a semiconductor substrate; b) a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; and c) a second polarity internal junction region entirely received within one of the first polarity regions. In yet another aspect, A resistor, comprising: a) a gate on a semiconductor substrate, the gate being electrically powered with a gate voltage; b) a first polarity source active region and a first polarity drain active region operatively adjacent the electrically powered gate; c) a second polarity internal junction region entirely received within one of the first polarity regions; and d) a current between the first polarity source active region and the first polarity drain active region, the current being substantially linearly dependent on a voltage at the drain region.

Abstract translation: 一方面，一种用于在半导体衬底上形成晶体管器件的方法，包括：a）在其上形成晶体管栅极。 基质; b）形成与晶体管栅极可操作地相邻的第一极性源极有源区和第一极性漏极有源区; 以及c）形成第二极性内部结合区域，所述第二极性内部结合区域完全接收在所述第一极性区域之一内。 在另一方面，一种晶体管器件，包括：a）半导体衬底上的晶体管栅极; b）可操作地邻近晶体管栅极的第一极性源极有源区和第一极性漏极有源区; 以及c）完全接收在所述第一极性区域之一内的第二极性内部连接区域。 在另一方面，一种电阻器，包括：a）半导体衬底上的栅极，栅极由栅极电压供电; b）第一极性源有源区和可操作地邻近电动门的第一极性漏极有源区; c）完全接收在所述第一极性区域之一内的第二极性内部连接区域; 以及d）所述第一极性源极活性区域和所述第一极性漏极有源区域之间的电流，所述电流基本上线性地取决于所述漏极区域处的电压。