公开(公告)号：US5043943A

公开(公告)日：1991-08-27

申请号：US539651

申请日：1990-06-18

申请人： Richard D. Crisp ,  Taisheng Feng ,  Jennifer Y. Chiao

发明人： Richard D. Crisp ,  Taisheng Feng ,  Jennifer Y. Chiao

IPC分类号： G06F11/10 ,  G06F12/08

CPC分类号： G06F11/1064 ,  G06F12/0802

摘要： A parity SRAM having the capability to support byte parity is provided. The parity SRAM uses four (4) independent byte write enable (BWE.sub.x) signals to enable a write amplifier to individually write a single parity bit to a selected memory location. The SRAM is designed to function in either a parity or a non-parity mode. A bonding option pad is connected to parity control logic circuitry, and determines whether the SRAM will function in the parity mode or the non-parity mode. The parity control logic circuitry generates a parity signal, based on the electrical connection of the option pad. Thus, when the option pad is connected to ground, the parity option is selected, whereas, when the option pad is connected to a positive power supply, then non-parity functionality is selected. When parity functionality is selected, the the SRAM will allow the four (4) independent BWE.sub.x signals to individually enable the write amplifier. When non-parity functionality is selected, a single control signal will enable the write amplifier, and the SRAM functions as a standard memory device.

摘要翻译： 提供了具有支持字节奇偶校验能力的奇偶校验SRAM。 奇偶校验SRAM使用四（4）个独立字节写使能（BWEx）信号，使写放大器可以将单个奇偶校验位单独写入所选存储单元。 SRAM被设计为以奇偶校验或非奇偶校验方式工作。 键合选项焊盘连接到奇偶校验控制逻辑电路，并确定SRAM是否将在奇偶校验模式或非奇偶校验模式下工作。 奇偶校验控制逻辑电路基于选件板的电连接产生奇偶校验信号。 因此，当选件焊盘连接到地时，选择奇偶选项，而当选件焊盘连接到正电源时，则选择非奇偶校验功能。 当选择奇偶校验功能时，SRAM将允许四（4）个独立BWEx信号单独启用写放大器。 当选择非奇偶校验功能时，单个控制信号将使能写入放大器，并且SRAM用作标准存储器件。

公开(公告)号：US4380707A

公开(公告)日：1983-04-19

申请号：US150536

申请日：1980-05-16

申请人： Richard D. Crisp

发明人： Richard D. Crisp

IPC分类号： H03K17/14 ,  H03K19/003 ,  H03K19/0185 ,  G05F1/56 ,  H03K17/687 ,  H03K19/094

CPC分类号： H03K19/018507 ,  H03K17/145 ,  H03K19/00384

摘要： An MOS input buffer circuit for receiving transistor transistor logic (T.sup.2 L) logic level input signal includes a plurality of inverting amplifier stages. The input signal is applied to the gate electrode of a first field effect transistor in the first inverter stage and may assume a high logic level of as low as 2 volts and a low logic level of as high as 0.8 volts. In order to provide a stable switching point at the output of the first inverter stage, a feedback field effect transistor is coupled between the output of the first inverter stage and ground and has its gate electrodes coupled to a source of supply voltage (V.sub.DD). As V.sub.DD increases, the feedback field effect transistor will sink more current and thus alter the gain of the first amplifying stage to stabilize its switch point. To further enhance the tracking capabilities over temperature and process variations, the first two inverter stages are comprised entirely of field effect transistors of the enhancement type and having substantially equal channel lengths.

摘要翻译： 用于接收晶体管晶体管逻辑（T2L）逻辑电平输入信号的MOS输入缓冲电路包括多个反相放大器级。 输入信号被施加到第一反相器级中的第一场效应晶体管的栅电极，并且可以采用低至2伏的高逻辑电平和高达0.8伏特的低逻辑电平。 为了在第一反相器级的输出端提供稳定的开关点，反馈场效应晶体管耦合在第一反相器级的输出端与地之间，其栅电极耦合到电源电压源（VDD）。 当VDD增加时，反馈场效应晶体管将吸收更多的电流，从而改变第一放大级的增益以稳定其开关点。 为了进一步增强温度和工艺变化的跟踪能力，前两个逆变器级完全由增强型的场效应晶体管组成并且具有基本相等的沟道长度。

公开(公告)号：US4578601A

公开(公告)日：1986-03-25

申请号：US559070

申请日：1983-12-07

申请人： Doyle V. McAlister ,  Richard D. Crisp

发明人： Doyle V. McAlister ,  Richard D. Crisp

IPC分类号： H03K19/017 ,  H03K19/0185 ,  H03K19/096

CPC分类号： H03K19/018521 ,  H03K19/01707

摘要： A buffer circuit is provided for buffering an input clock signal having TTL voltage levels to provide an output clock signal having MOS voltage levels. A reference voltage portion provides an accurate bias voltage to a first node. A voltage translation portion is coupled between an input and the first node. An inverter portion has a first input connected to the first node, a second input for receiving the input clock signal, and an output for providing the output clock signal. A clamping portion is connected to the first node to minimize the bias voltage potential.

摘要翻译： 提供缓冲电路用于缓冲具有TTL电压电平的输入时钟信号，以提供具有MOS电压电平的输出时钟信号。 参考电压部分向第一节点提供精确的偏置电压。 电压转换部分耦合在输入端和第一节点之间。 逆变器部分具有连接到第一节点的第一输入端，用于接收输入时钟信号的第二输入端和用于提供输出时钟信号的输出端。 钳位部分连接到第一节点以最小化偏置电压电位。

公开(公告)号：US4488256A

公开(公告)日：1984-12-11

申请号：US330051

申请日：1981-12-14

申请人： John E. Zolnowsky ,  William M. Keshlear ,  Richard D. Crisp

发明人： John E. Zolnowsky ,  William M. Keshlear ,  Richard D. Crisp

IPC分类号： G06F12/10 ,  G06F12/14 ,  G06F13/00

CPC分类号： G06F12/1475 ,  G06F12/1036

摘要： A memory management unit of use in a memory management system. The memory management unit selectively maps a logical address to a respective physical address in accordance with a selected one of a plurality of segment descriptors, each of which defines a logical-to-physical address mapping and a range of address spaces for which such mapping is valid. The mapping is achieved using an improved associative memory circuit. Means are provided to detect mapping conflicts between new segment descriptors and segment descriptors already stored, and to prevent the storage of such conflicting segment descriptors. A method and circuit are provided to coordinate the parallel operation of a plurality of the memory management units or the like.

摘要翻译： 一种在存储器管理系统中使用的存储器管理单元。 存储器管理单元根据多个段描述符中的所选择的一个段描述符来选择性地将逻辑地址映射到相应的物理地址，每个区段描述符定义了逻辑到物理地址映射以及一定范围的地址空间， 有效。 使用改进的关联存储器电路实现映射。 提供了用于检测已经存储的新的段描述符和段描述符之间的映射冲突的手段，并且防止存储这种冲突的段描述符。 提供了一种方法和电路来协调多个存储器管理单元等的并行操作。

公开(公告)号：US4918663A

公开(公告)日：1990-04-17

申请号：US97029

申请日：1987-09-16

申请人： Scott I. Remington ,  Richard D. Crisp

发明人： Scott I. Remington ,  Richard D. Crisp

IPC分类号： G11C11/4072 ,  G11C11/4091

CPC分类号： G11C11/4091 ,  G11C11/4072

摘要： A CMOS DRAM has an array in a well which is pumped to a voltage greater than the power supply voltage. The transfer devices of the memory cells in the array are of a conductivity type opposite to that of the well. The transfer devices each have a source/drain of the opposite conductivity type to that of the well which is connected to a bit line. The bit line will tend to rise in voltage at power-up which has the potential of forward biasing the PN junction between the source/drain and the well. The bit line rise is due to a word-line rise the rate of which is controlled so that the bit line rise does not exceed the rise in array voltage. The bit lines are ensured of being separated in voltage at the beginning of the first active cycle by enabling the N channel portion of the sense amplifier during power-up. The P channel portion of the sense amplifier is disabled during power-up to avoid too rapid of a rise in voltage on the bit lines. Equalization of the bit lines is suppressed during the first cycle to avoid having the sense amplifier face the high current drain condition of little or no voltage differential at low voltage.

摘要翻译： CMOS DRAM在井中具有被泵送到大于电源电压的电压的阵列。 阵列中存储单元的转移装置的导电类型与孔的导电类型相反。 转移装置各自具有与连接到位线的阱的相反导电类型的源极/漏极。 在上电时，位线将趋于上升，其具有正向偏置源极/漏极和阱之间的PN结的潜力。 位线上升是由于其速率被控制的字线上升，使得位线上升不超过阵列电压的上升。 通过在上电期间启用读出放大器的N沟道部分，确保位线在第一有效周期开始时被分离成电压。 在上电期间，读出放大器的P沟道部分被禁止，以避免位线上的电压上升太快。 在第一周期期间抑制了位线的均衡，以避免在低电压下，感测放大器面临很小或没有电压差的高电流漏极条件。

公开(公告)号：US4907189A

公开(公告)日：1990-03-06

申请号：US229201

申请日：1988-08-08

申请人： Brian D. Branson ,  Richard D. Crisp

发明人： Brian D. Branson ,  Richard D. Crisp

IPC分类号： G06F12/08

CPC分类号： G06F12/0895

摘要： A cache TAG, which has a compare mode, an and/or/invert mode, and a read mode, has a programmable comparator which receives an external data signal and an output from an array of memory cells and provides an output to a secondary amplifier. The secondary amplifier provides an output to a match comparator in the compare mode and the and/or/invert mode and to an output buffer in the read mode. The programmable comparator is programmable according to the mode of the cache TAG. The compartor uses selectively enabled transmission gates which provide minimal delay in providing the appropriate data to the secondary sense amplifiers.

摘要翻译： 具有比较模式，/或/反转模式和读取模式的高速缓存TAG具有可编程比较器，其接收来自存储器单元阵列的外部数据信号和输出，并向次级放大器提供输出 。 次级放大器在比较模式和/或/反相模式下向匹配比较器提供输出，并以读取模式向输出缓冲器提供输出。 可编程比较器可根据缓存TAG的模式进行编程。 compartor使用有选择地使能的传输门，这些传输门在向次级感测放大器提供适当的数据时提供最小的延迟。

公开(公告)号：US4866676A

公开(公告)日：1989-09-12

申请号：US172514

申请日：1988-03-24

申请人： Richard D. Crisp ,  George P. Hoekstra ,  George G. Watkins

发明人： Richard D. Crisp ,  George P. Hoekstra ,  George G. Watkins

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24 ,  G11C29/36

CPC分类号： G11C29/78 ,  G11C29/24 ,  G11C29/36

摘要： A read/write memory has bit line pairs variously having a first or a second true/complement orientation. Data is selectively coupled to and from the bit line pairs to and from a data line pair via a column decoder. The memory has redundant bit line pairs aligned in the first true/complement arrangement. When a redundant bit line pair is implemented, the logic state of the data is inverted both for reading and for writing if the replaced bit line pair is of the second true/complement orientation. This results in the voltage impressed onto the memory cell for a given logic state is the same for the redundant bit line pair as for the bit line pair that it replaced.

公开(公告)号：US4449064A

公开(公告)日：1984-05-15

申请号：US250522

申请日：1981-04-02

申请人： Kim Eckert ,  Richard D. Crisp ,  Lam Ta

发明人： Kim Eckert ,  Richard D. Crisp ,  Lam Ta

IPC分类号： H03K19/094 ,  H03K19/017

CPC分类号： H03K19/09429

摘要： A three state output circuit which pulls down the output node thereof to a first supply voltage in response to an assert signal, pulls up the output node to a second supply voltage in response to a rescind signal, and then presents a high impedance on the output node immediately after the output node is pulled up to a selected reference voltage.

摘要翻译： 三状态输出电路，其响应于断言信号将其输出节点向下拉到第一电源电压，响应于重新取消信号将输出节点拉至第二电源电压，然后在输出端呈现高阻抗 在将输出节点上拉到所选择的参考电压之后的节点。