公开(公告)号：US08536914B2

公开(公告)日：2013-09-17

申请号：US13033057

申请日：2011-02-23

Applicant: Ji Hun Oh ,  Donghwan Lee

Inventor： Ji Hun Oh ,  Donghwan Lee

IPC: H03L7/06

CPC classification number: H03L7/06

Abstract: Provided are a delay locked loop (DLL), which is capable of being adopted at a data processing system and include a duty correction circuit, and a duty correction method at the DLL. The duty correction method includes generating first and second delay clock signals having different phase shifts by delaying an external clock signal by as much as first and second set phases in response to a delay control signal, generating first and second first signals respectively synchronized with the first and second delay clock signals, and generating an output clock signal having a set duty ratio by using the first and second pulse signals. According to the foregoing, a more accurate duty correction operation is performed without a half cycle time delay line or a matching delay line.

Abstract translation: 提供了一种延迟锁定环（DLL），其能够在数据处理系统中被采用，并且包括在DLL处的占空比校正电路和占空比校正方法。 占空比校正方法包括响应于延迟控制信号，通过将外部时钟信号延迟多达第一和第二设定相位而产生具有不同相移的第一和第二延迟时钟信号，产生分别与第一和第二设定相位同步的第一和第二第一信号 和第二延迟时钟信号，并且通过使用第一和第二脉冲信号产生具有设定占空比的输出时钟信号。 根据上述，在没有半周期时间延迟线或匹配延迟线的情况下执行更精确的占空比校正操作。

公开(公告)号：US20100219867A1

公开(公告)日：2010-09-02

申请号：US12659010

申请日：2010-02-23

Applicant: Jong-Ryun Choi ,  Dong Hwan Lee ,  Su Ho Kim ,  Won Lee ,  Alex Joo ,  Ji Hun Oh

Inventor： Jong-Ryun Choi ,  Dong Hwan Lee ,  Su Ho Kim ,  Won Lee ,  Alex Joo ,  Ji Hun Oh

IPC: H03L7/06

CPC classification number: H03L7/0814 ,  H03L7/0805 ,  H03L7/0818 ,  H03L7/10

Abstract: A delay locked loop is provided. The delay locked loop controls the number of delay cells that delay the phase of an input clock during a locking operation and controls a phase delay value of at least one delay cell among a plurality of delay cells after the locking operation is completed.

Abstract translation: 提供延迟锁定环。 延迟锁定环控制在锁定操作期间延迟输入时钟的相位的延迟单元的数量，并且在锁定操作完成之后控制多个延迟单元中的至少一个延迟单元的相位延迟值。

公开(公告)号：US06723587B2

公开(公告)日：2004-04-20

申请号：US10331568

申请日：2002-12-31

Applicant: Won-Ju Cho ,  Jong-Heon Yang ,  Moon-Gyu Jang ,  Seong-Jae Lee ,  Kyoung-Wan Park ,  Ki-Ju Im ,  Ji-Hun Oh

Inventor： Won-Ju Cho ,  Jong-Heon Yang ,  Moon-Gyu Jang ,  Seong-Jae Lee ,  Kyoung-Wan Park ,  Ki-Ju Im ,  Ji-Hun Oh

IPC: H01L2184

CPC classification number: H01L29/78696 ,  H01L29/66772 ,  H01L29/78609

Abstract: An ultra small-sized SOI MOSFET having a high integration density, low power consumption, but high performances, and a method of fabricating the same are provided. The method includes preparing a SOI substrate on which a monocrystalline silicon layer is formed, forming a first dielectric material layer doped with impurities of a first conductivity type on the SOI substrate, forming an opening to expose the monocrystalline silicon layer etching at least part of the first dielectric material layer, forming a channel region injecting impurities of a second conductivity type into the monocrystalline silicon layer exposed by the opening, forming a source region and a drain region in the monocrystalline silicon layer diffusing the impurities of the first dielectric material layer using heat treatment, forming a gate dielectric layer in the opening on the channel region, forming a gate electrode on the gate dielectric layer to fit in the opening, forming a second dielectric material layer on the entire surface of the SOI substrate on which the gate electrode is formed, forming contact holes to expose the gate electrode, the source region, and the drain region etching part of the second dielectric material layer, and forming metal interconnections to bury the contact holes.

Abstract translation: 提供了具有高积分密度，低功耗但高性能的超小尺寸SOI MOSFET及其制造方法。 该方法包括制备在其上形成单晶硅层的SOI衬底，在SOI衬底上形成掺杂有第一导电类型的杂质的第一介电材料层，形成开口，以暴露单晶硅层，刻蚀至少部分 第一介电材料层，形成将由第二导电类型杂质注入由开口露出的单晶硅层的沟道区，在单晶硅层中形成源极区和漏极区，使用热量扩散第一介电材料层的杂质 在沟道区域的开口中形成栅极电介质层，在栅极电介质层上形成栅电极以配合在开口中，在栅极电极的SOI衬底的整个表面上形成第二电介质层 形成，形成接触孔以露出栅电极，源极区和漏极 区域蚀刻第二介电材料层的部分，以及形成用于埋入接触孔的金属互连。

公开(公告)号：US08283958B2

公开(公告)日：2012-10-09

申请号：US12659010

申请日：2010-02-23

Applicant: Jong-Ryun Choi ,  Dong Hwan Lee ,  Su Ho Kim ,  Won Lee ,  Alex Joo ,  Ji Hun Oh

Inventor： Jong-Ryun Choi ,  Dong Hwan Lee ,  Su Ho Kim ,  Won Lee ,  Alex Joo ,  Ji Hun Oh

IPC: H03L7/06

CPC classification number: H03L7/0814 ,  H03L7/0805 ,  H03L7/0818 ,  H03L7/10

Abstract: A delay locked loop is provided. The delay locked loop controls the number of delay cells that delay the phase of an input clock during a locking operation and controls a phase delay value of at least one delay cell among a plurality of delay cells after the locking operation is completed.

Abstract translation: 提供延迟锁定环。 延迟锁定环控制在锁定操作期间延迟输入时钟的相位的延迟单元的数量，并且在锁定操作完成之后控制多个延迟单元中的至少一个延迟单元的相位延迟值。

公开(公告)号：US20110215851A1

公开(公告)日：2011-09-08

申请号：US13033057

申请日：2011-02-23

Applicant: Ji Hun OH ,  Donghwan Lee

Inventor： Ji Hun OH ,  Donghwan Lee

IPC: H03L7/06

CPC classification number: H03L7/06

Abstract: Provided are a delay locked loop (DLL), which is capable of being adopted at a data processing system and include a duty correction circuit, and a duty correction method at the DLL. The duty correction method includes generating first and second delay clock signals having different phase shifts by delaying an external clock signal by as much as first and second set phases in response to a delay control signal, generating first and second first signals respectively synchronized with the first and second delay clock signals, and generating an output clock signal having a set duty ratio by using the first and second pulse signals. According to the foregoing, a more accurate duty correction operation is performed without a half cycle time delay line or a matching delay line.

Abstract translation: 提供了一种延迟锁定环（DLL），其能够在数据处理系统中被采用，并且包括占空比校正电路和DLL处的占空比校正方法。 占空比校正方法包括响应于延迟控制信号，通过将外部时钟信号延迟多达第一和第二设定相位而产生具有不同相移的第一和第二延迟时钟信号，产生分别与第一和第二设定相位同步的第一和第二第一信号 和第二延迟时钟信号，并且通过使用第一和第二脉冲信号产生具有设定占空比的输出时钟信号。 根据上述，在没有半周期时间延迟线或匹配延迟线的情况下执行更精确的占空比校正操作。