利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

78 条记录 (耗时 0.039 秒)

    Ultra small-sized SOI MOSFET and method of fabricating the same
    1.
    发明授权
    Ultra small-sized SOI MOSFET and method of fabricating the same 有权
    超小型SOI MOSFET及其制造方法

    公开(公告)号：US06723587B2

    公开(公告)日：2004-04-20

    申请号：US10331568

    申请日：2002-12-31

    申请人： Won-Ju Cho ,  Jong-Heon Yang ,  Moon-Gyu Jang ,  Seong-Jae Lee ,  Kyoung-Wan Park ,  Ki-Ju Im ,  Ji-Hun Oh

    发明人： Won-Ju Cho ,  Jong-Heon Yang ,  Moon-Gyu Jang ,  Seong-Jae Lee ,  Kyoung-Wan Park ,  Ki-Ju Im ,  Ji-Hun Oh

    IPC分类号： H01L2184

    CPC分类号： H01L29/78696 ,  H01L29/66772 ,  H01L29/78609

    摘要： An ultra small-sized SOI MOSFET having a high integration density, low power consumption, but high performances, and a method of fabricating the same are provided. The method includes preparing a SOI substrate on which a monocrystalline silicon layer is formed, forming a first dielectric material layer doped with impurities of a first conductivity type on the SOI substrate, forming an opening to expose the monocrystalline silicon layer etching at least part of the first dielectric material layer, forming a channel region injecting impurities of a second conductivity type into the monocrystalline silicon layer exposed by the opening, forming a source region and a drain region in the monocrystalline silicon layer diffusing the impurities of the first dielectric material layer using heat treatment, forming a gate dielectric layer in the opening on the channel region, forming a gate electrode on the gate dielectric layer to fit in the opening, forming a second dielectric material layer on the entire surface of the SOI substrate on which the gate electrode is formed, forming contact holes to expose the gate electrode, the source region, and the drain region etching part of the second dielectric material layer, and forming metal interconnections to bury the contact holes.

    摘要翻译： 提供了具有高积分密度，低功耗但高性能的超小尺寸SOI MOSFET及其制造方法。 该方法包括制备在其上形成单晶硅层的SOI衬底，在SOI衬底上形成掺杂有第一导电类型的杂质的第一介电材料层，形成开口，以暴露单晶硅层，刻蚀至少部分 第一介电材料层，形成将由第二导电类型杂质注入由开口露出的单晶硅层的沟道区，在单晶硅层中形成源极区和漏极区，使用热量扩散第一介电材料层的杂质 在沟道区域的开口中形成栅极电介质层，在栅极电介质层上形成栅电极以配合在开口中，在栅极电极的SOI衬底的整个表面上形成第二电介质层 形成，形成接触孔以露出栅电极，源极区和漏极 区域蚀刻第二介电材料层的部分，以及形成用于埋入接触孔的金属互连。

    Schottky barrier tunnel transistor using thin silicon layer on insulator and method for fabricating the same
    2.
    发明授权
    Schottky barrier tunnel transistor using thin silicon layer on insulator and method for fabricating the same 失效
    使用绝缘体上的薄硅层的肖特基势垒隧道晶体管及其制造方法

    公开(公告)号：US06693294B1

    公开(公告)日：2004-02-17

    申请号：US10331945

    申请日：2002-12-31

    申请人： Moon-Gyu Jang ,  Seong-Jae Lee ,  Woo-Seok Cheong ,  Won-Ju Cho ,  Kyoung-Wan Park

    发明人： Moon-Gyu Jang ,  Seong-Jae Lee ,  Woo-Seok Cheong ,  Won-Ju Cho ,  Kyoung-Wan Park

    IPC分类号： H01L3900

    CPC分类号： H01L29/42384 ,  H01L29/458 ,  H01L29/7839 ,  H01L29/78609 ,  H01L29/78696

    摘要： Provided are a Schottky barrier tunnel transistor (SBTT) and a method of fabricating the same. The SBTT includes a buried oxide layer formed on a base substrate layer and having a groove at its upper surface; an ultra-thin silicon-on-insulator (SOI) layer formed across the groove; an insulating layer wrapping the SOI layer on the groove; a gate formed to be wider than the groove on the insulating layer; source and drain regions each positioned at both sides of the gate, the source and drain regions formed of silicide; and a conductive layer for filling the groove. In the SBTT, the SOI layer is formed to an ultra-thin thickness to minimize the occurrence of a leakage current, and a channel in the SOI layer below the gate is completely wrapped by the gate and the conductive layer, thereby improving the operational characteristics of the SBTT.

    摘要翻译： 提供了一种肖特基势垒隧道晶体管（SBTT）及其制造方法。 SBTT包括形成在基底层上并在其上表面具有凹槽的掩埋氧化物层; 跨越沟槽形成的超薄绝缘体上硅（SOI）层; 将SOI层包裹在槽上的绝缘层; 形成为比绝缘层上的沟槽宽的栅极; 源极和漏极区域各自位于栅极的两侧，源极和漏极区域由硅化物形成; 以及用于填充凹槽的导电层。 在SBTT中，SOI层形成为超薄的厚度，以最小化泄漏电流的发生，栅极下方的SOI层中的沟道被栅极和导电层完全包围，从而提高了操作特性 的SBTT。

    METHOD FOR FABRICATING SCHOTTKY BARRIER TUNNEL TRANSISTOR
    3.
    发明申请
    METHOD FOR FABRICATING SCHOTTKY BARRIER TUNNEL TRANSISTOR 失效
    用于制作肖特基栅栏隧道晶体管的方法

    公开(公告)号：US20080132049A1

    公开(公告)日：2008-06-05

    申请号：US11930902

    申请日：2007-10-31

    申请人： Yark-Yeon KIM ,  Seong-Jae Lee ,  Moon-Gyu Jang ,  Tae-Youb Kim ,  Chel-Jong Choi ,  Myung-Sim Jun ,  Byoung-Chul Park

    发明人： Yark-Yeon KIM ,  Seong-Jae Lee ,  Moon-Gyu Jang ,  Tae-Youb Kim ,  Chel-Jong Choi ,  Myung-Sim Jun ,  Byoung-Chul Park

    IPC分类号： H01L21/334

    CPC分类号： H01L29/78618 ,  H01L29/7839

    摘要： Provided is a method for fabricating a Schottky barrier tunnel transistor (SBTT) that can fundamentally prevent the generation of a gate leakage current caused by damage of spacers formed on both sidewalls of a gate electrode. The method for fabricating a Schottky barrier tunnel transistor, which includes: a) forming a silicon pattern and a sacrificial pattern on a buried oxide layer supported by a support substrate; b) forming a source/drain region on the buried oxide layer exposed on both sides of the silicon pattern, the source/drain region being formed of a metal layer and being in contact with both sidewalls of the silicon pattern; c) removing the sacrificial pattern to expose the top surface of the silicon pattern; and d) forming a gate insulating layer and a gate electrode on the exposed silicon pattern.

    摘要翻译： 提供一种用于制造肖特基势垒隧道晶体管（SBTT）的方法，其可以从根本上防止由栅极电极的两个侧壁上形成的间隔物的损坏引起的栅极漏电流的产生。 一种制造肖特基势垒隧道晶体管的方法，包括：a）在由支撑衬底支撑的掩埋氧化物层上形成硅图案和牺牲图案; b）在暴露于硅图案的两侧的掩埋氧化物层上形成源极/漏极区域，源极/漏极区域由金属层形成并与硅图案的两个侧壁接触; c）去除牺牲图案以暴露硅图案的顶表面; 以及d）在暴露的硅图案上形成栅极绝缘层和栅电极。

    Method for fabricating Schottky barrier tunnel transistor
    6.
    发明授权
    Method for fabricating Schottky barrier tunnel transistor 失效
    制造肖特基势垒隧道晶体管的方法

    公开(公告)号：US07745316B2

    公开(公告)日：2010-06-29

    申请号：US11930902

    申请日：2007-10-31

    申请人： Yark-Yeon Kim ,  Seong-Jae Lee ,  Moon-Gyu Jang ,  Tae-Youb Kim ,  Chel-Jong Choi ,  Myung-Sim Jun ,  Byoung-Chul Park

    发明人： Yark-Yeon Kim ,  Seong-Jae Lee ,  Moon-Gyu Jang ,  Tae-Youb Kim ,  Chel-Jong Choi ,  Myung-Sim Jun ,  Byoung-Chul Park

    IPC分类号： H01L21/28 ,  H01L21/44

    CPC分类号： H01L29/78618 ,  H01L29/7839

    摘要： Provided is a method for fabricating a Schottky barrier tunnel transistor (SBTT) that can fundamentally prevent the generation of a gate leakage current caused by damage of spacers formed on both sidewalls of a gate electrode. The method for fabricating a Schottky barrier tunnel transistor, which includes: a) forming a silicon pattern and a sacrificial pattern on a buried oxide layer supported by a support substrate; b) forming a source/drain region on the buried oxide layer exposed on both sides of the silicon pattern, the source/drain region being formed of a metal layer and being in contact with both sidewalls of the silicon pattern; c) removing the sacrificial pattern to expose the top surface of the silicon pattern; and d) forming a gate insulating layer and a gate electrode on the exposed silicon pattern.

    摘要翻译： 提供一种用于制造肖特基势垒隧道晶体管（SBTT）的方法，其可以从根本上防止由栅极电极的两个侧壁上形成的间隔物的损坏引起的栅极漏电流的产生。 一种制造肖特基势垒隧道晶体管的方法，包括：a）在由支撑衬底支撑的掩埋氧化物层上形成硅图案和牺牲图案; b）在暴露于硅图案的两侧的掩埋氧化物层上形成源极/漏极区域，源极/漏极区域由金属层形成并与硅图案的两个侧壁接触; c）去除牺牲图案以暴露硅图案的顶表面; 以及d）在暴露的硅图案上形成栅极绝缘层和栅电极。

    Apparatus for manufacturing semiconductor device and method for manufacturing semiconductor device by using the same
    8.
    发明申请
    Apparatus for manufacturing semiconductor device and method for manufacturing semiconductor device by using the same 审中-公开
    半导体装置的制造装置及其制造方法

    公开(公告)号：US20060048706A1

    公开(公告)日：2006-03-09

    申请号：US10527056

    申请日：2002-12-30

    申请人： Woo-Seok Cheong ,  Seong-Jae Lee ,  Won-Ju Jo ,  Moon-Gyu Jang

    发明人： Woo-Seok Cheong ,  Seong-Jae Lee ,  Won-Ju Jo ,  Moon-Gyu Jang

    IPC分类号： C23C16/00

    CPC分类号： H01L21/67207 ,  H01L29/66848

    摘要： In a process for manufacturing a hyperfine semiconductor device, an apparatus for manufacturing a semiconductor device such as a schottky barrier MOSFET and a method for manufacturing the semiconductor device using the same are provided. Two chambers are connected with each other. A cleaning process, a metal layer forming process, and subsequent processes can be performed in situ by using the two chambers, thereby the attachment of the unnecessary impurities and the formation of the oxide can be prevented and the optimization of the process can be accomplished.

    摘要翻译： 在制造超精细半导体器件的方法中，提供了用于制造诸如肖特基势垒MOSFET的半导体器件的装置以及使用其制造半导体器件的方法。 两个腔室相互连接。 可以通过使用两个室来原位进行清洁处理，金属层形成工艺和随后的工艺，从而可以防止不必要的杂质的附着和氧化物的形成，并且可以实现工艺的优化。

    Ultra-thin MO-C film transistor
    9.
    发明授权
    Ultra-thin MO-C film transistor 失效
    超薄MO-C薄膜晶体管

    公开(公告)号：US5883419A

    公开(公告)日：1999-03-16

    申请号：US850013

    申请日：1997-05-01

    申请人： Seong-Jae Lee ,  Kyoung-Wan Park ,  Min-Cheol Shin

    发明人： Seong-Jae Lee ,  Kyoung-Wan Park ,  Min-Cheol Shin

    IPC分类号： H01L41/00 ,  H01L45/00 ,  B02J17/40 ,  B05D3/06

    CPC分类号： H01L45/00

    摘要： A transistor in accordance with the invention comprises an ultra-thin Mo--C film functioning as a channel for an electron flow with two ends of the thin metal film functioning as source and drain terminals of the transistor, respectively; a piezoelectric film formed on the Mo--C film, for producing a force in accordance with an applied electric field provided by a gate voltage; and an electrode film formed on the piezoelectric film functioning as a gate of the transistor to which the gate voltage is applied to produce the applied electric field; and wherein a resistance of the Mo--C film between the source and drain terminals changes in accordance with the force produced in response to the applied gate voltage. This transistor can be used as an element of the three dimensional integrated circuit with a laminated structure.

    摘要翻译： 根据本发明的晶体管包括用作电子流的通道的超薄Mo-C膜，其中薄金属膜的两端分别用作晶体管的源极和漏极端子; 形成在Mo-C膜上的压电膜，用于根据由栅极电压提供的施加的电场产生力; 以及形成在作为施加栅极电压的晶体管的栅极的压电膜上产生施加的电场的电极膜; 并且其中源极和漏极端子之间的Mo-C膜的电阻根据施加的栅极电压产生的力而改变。 该晶体管可以用作具有层叠结构的三维集成电路的元件。