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公开(公告)号:US20160276485A1
公开(公告)日:2016-09-22
申请号:US14984284
申请日:2015-12-30
申请人: Ju-youn KIM , Sang-jung KANG , Ji-hwan AN
发明人: Ju-youn KIM , Sang-jung KANG , Ji-hwan AN
IPC分类号: H01L29/78 , H01L29/423 , H01L29/06
CPC分类号: H01L27/0886 , H01L21/823431 , H01L29/0649 , H01L29/42376 , H01L29/66545 , H01L29/66795 , H01L29/7856
摘要: A semiconductor device includes at least one first gate structure and at least one second gate structure on a semiconductor substrate. The at least one first gate structure has a flat upper surface extending in a first direction and a first width in a second direction perpendicular to the first direction. The at least one second gate structure has a convex upper surface extending in the first direction and a second width in the second direction, the second width being greater than the first width.
摘要翻译: 半导体器件包括半导体衬底上的至少一个第一栅极结构和至少一个第二栅极结构。 所述至少一个第一栅极结构具有在第一方向上延伸的平坦的上表面和在垂直于第一方向的第二方向上的第一宽度。 所述至少一个第二栅极结构具有在所述第一方向上延伸的凸上表面和在所述第二方向上延伸的第二宽度,所述第二宽度大于所述第一宽度。
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公开(公告)号:US09614090B2
公开(公告)日:2017-04-04
申请号:US14984284
申请日:2015-12-30
申请人: Ju-youn Kim , Sang-jung Kang , Ji-hwan An
发明人: Ju-youn Kim , Sang-jung Kang , Ji-hwan An
IPC分类号: H01L29/78 , H01L29/66 , H01L29/06 , H01L29/423
CPC分类号: H01L27/0886 , H01L21/823431 , H01L29/0649 , H01L29/42376 , H01L29/66545 , H01L29/66795 , H01L29/7856
摘要: A semiconductor device includes at least one first gate structure and at least one second gate structure on a semiconductor substrate. The at least one first gate structure has a flat upper surface extending in a first direction and a first width in a second direction perpendicular to the first direction. The at least one second gate structure has a convex upper surface extending in the first direction and a second width in the second direction, the second width being greater than the first width.
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公开(公告)号:US20150357426A1
公开(公告)日:2015-12-10
申请号:US14621440
申请日:2015-02-13
申请人: JU-YOUN KIM , JI-HWAN AN , KWANG-YUL LEE , TAE-WON HA , JEONG-NAM HAN
发明人: JU-YOUN KIM , JI-HWAN AN , KWANG-YUL LEE , TAE-WON HA , JEONG-NAM HAN
IPC分类号: H01L29/423 , H01L21/324 , H01L21/8234 , H01L29/66 , H01L29/49 , H01L21/28 , H01L21/311
CPC分类号: H01L21/82345 , H01L21/28088 , H01L21/28185 , H01L21/31138 , H01L21/32139 , H01L21/823431 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66795
摘要: A method of fabricating a semiconductor device includes forming an inter-metal dielectric layer including a first trench and a second trench which are spaced from each other on a substrate, forming a first dielectric layer along the sides and bottom of the first trench, forming a second dielectric layer along the sides and bottom of the second trench, forming first and second lower conductive layers on the first and second dielectric layers, respectively, forming first and second capping layers on the first and second lower conductive layer, respectively, performing a heat treatment after the first and second capping layers have been formed, removing the first and second capping layers and the first and second lower conductive layers after performing the heat treatment, and forming first and second metal gate structures on the first and second dielectric layers, respectively.
摘要翻译: 一种制造半导体器件的方法包括形成包括第一沟槽和第二沟槽的金属间电介质层,所述第一沟槽和第二沟槽在衬底上彼此间隔开,沿着第一沟槽的侧面和底部形成第一电介质层, 第二介电层,分别在第一和第二介电层上形成第一和第二下导电层,分别在第一和第二下导电层上形成第一和第二封盖层,进行热处理 在形成第一和第二封盖层之后的处理,在进行热处理之后去除第一和第二封盖层以及第一和第二下导电层,并分别在第一和第二电介质层上形成第一和第二金属栅极结构 。
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公开(公告)号:US09812367B2
公开(公告)日:2017-11-07
申请号:US14621440
申请日:2015-02-13
申请人: Ju-Youn Kim , Ji-Hwan An , Kwang-Yul Lee , Tae-Won Ha , Jeong-Nam Han
发明人: Ju-Youn Kim , Ji-Hwan An , Kwang-Yul Lee , Tae-Won Ha , Jeong-Nam Han
IPC分类号: H01L21/8234 , H01L29/66 , H01L29/51 , H01L21/28 , H01L29/49 , H01L21/311 , H01L21/3213
CPC分类号: H01L21/82345 , H01L21/28088 , H01L21/28185 , H01L21/31138 , H01L21/32139 , H01L21/823431 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66795
摘要: A method of fabricating a semiconductor device includes forming an inter-metal dielectric layer including a first trench and a second trench which are spaced from each other on a substrate, forming a first dielectric layer along the sides and bottom of the first trench, forming a second dielectric layer along the sides and bottom of the second trench, forming first and second lower conductive layers on the first and second dielectric layers, respectively, forming first and second capping layers on the first and second lower conductive layer, respectively, performing a heat treatment after the first and second capping layers have been formed, removing the first and second capping layers and the first and second lower conductive layers after performing the heat treatment, and forming first and second metal gate structures on the first and second dielectric layers, respectively.
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