公开(公告)号：US20120056258A1

公开(公告)日：2012-03-08

申请号：US13226218

申请日：2011-09-06

申请人： Shu-Lu CHEN

发明人： Shu-Lu CHEN

IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/76254 ,  H01L21/823828 ,  H01L27/0688 ,  H01L29/66621 ,  H01L29/7838 ,  H01L29/78654 ,  H01L2924/0002 ,  Y02P80/30 ,  H01L2924/00

摘要： An electrical switch using a gated resistor structure includes an isolation layer, a doped silicon layer arranged on the isolation layer and having a recessed portion with reduced thickness, the doped silicon layer having a predetermined doping type and a predetermined doping profile; a gate layer arranged corresponding to the recessed portion. The recessed portion in the doped silicon layer has such thickness that a channel defined under the gate can be fully depleted to form a high resistivity region. The recessed channel gated resistor structure can be advantageously used to achieve high interconnect density with low thermal budget for 3D integration.

摘要翻译： 使用门控电阻器结构的电开关包括隔离层，布置在隔离层上的掺杂硅层，并具有厚度减小的凹陷部分，掺杂硅层具有预定的掺杂类型和预定的掺杂分布; 对应于所述凹部布置的栅极层。 掺杂硅层中的凹陷部分具有这样的厚度，使得限定在栅极下方的沟道可以完全耗尽以形成高电阻率区域。 凹陷通道门控电阻器结构可以有利地用于实现具有低热预算的高互连密度以用于3D集成。

公开(公告)号：US20090176353A1

公开(公告)日：2009-07-09

申请号：US12392261

申请日：2009-02-25

申请人： James D. Plummer ,  Peter B. Griffin ,  Jia Feng ,  Shu-Lu Chen

发明人： James D. Plummer ,  Peter B. Griffin ,  Jia Feng ,  Shu-Lu Chen

IPC分类号： H01L21/208 ,  H01L21/20

CPC分类号： H01L29/66742 ,  B82Y10/00 ,  H01L21/02433 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02667 ,  H01L21/02675 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78684

摘要： Single-crystalline growth is realized using a liquid-phase crystallization approach involving the inhibition of defects typically associated with liquid-phase crystalline growth of lattice mismatched materials. According to one example embodiment, a semiconductor device structure includes a substantially single-crystal region. A liquid-phase material, such as Ge or a semiconductor compound, is crystallized to form the single-crystal region using an approach involving defect inhibition for the promotion of single-crystalline growth. In some instances, this defect inhibition involves the reduction and/or elimination of defects using a relatively small physical opening via which a crystalline growth front propagates. In other instances, this defect inhibition involves causing a change in crystallization front direction relative to a crystallization seed location. The relatively small physical opening and/or the change in crystalline front direction may be implemented, for example, using a material that is substantially unreactive with the liquid-phase material to contain the crystalline growth.

摘要翻译： 使用液相结晶方法实现单晶生长，其涉及通常与晶格失配材料的液相晶体生长相关的缺陷的抑制。 根据一个示例性实施例，半导体器件结构包括基本单晶区域。 使用涉及促进单晶生长的缺陷抑制的方法，使诸如Ge或半导体化合物的液相材料结晶形成单晶区域。 在一些情况下，该缺陷抑制包括使用晶体生长前沿传播的相对小的物理开口来减少和/或消除缺陷。 在其他情况下，该缺陷抑制涉及相对于结晶种子位置导致结晶前沿方向的变化。 可以例如使用与液相材料基本上不反应的材料以包含结晶生长来实现相对较小的物理开口和/或晶体前端方向的变化。

公开(公告)号：US08283730B2

公开(公告)日：2012-10-09

申请号：US12472345

申请日：2009-05-26

申请人： Shu-Lu Chen

发明人： Shu-Lu Chen

IPC分类号： H01L21/70

CPC分类号： H01L27/1203 ,  G11C11/39 ,  H01L27/092 ,  H01L27/11 ,  Y10T29/41

摘要： A negative differential resistance (NDR) device is designed and a possible compact device implementation is presented. The NDR device includes a voltage blocker and a current blocker and exhibits high peak-to-valley current ratio (PVCR) as well as high switching speed. The corresponding process and design are completely compatible with contemporary Si CMOS technology and area efficient. A single-NDR element SRAM cell prototype with a compact size and high speed is also proposed as its application suitable for embedded memory.

摘要翻译： 设计了负差分电阻（NDR）器件，并提出了可能的紧凑型器件实现。 NDR器件包括电压阻断器和电流阻断器，并且具有高的峰谷电流比（PVCR）以及高切换速度。 相应的工艺和设计与当今的Si CMOS技术和区域高效完全兼容。 还提出具有紧凑尺寸和高速度的单NDR元件SRAM单元原型作为其适用于嵌入式存储器的应用。

公开(公告)号：US20150037048A1

公开(公告)日：2015-02-05

申请号：US14129181

申请日：2013-08-02

申请人： Yun-Chung Na ,  Han-Din Liu ,  Yimin Kang ,  Shu-Lu Chen

发明人： Yun-Chung Na ,  Han-Din Liu ,  Yimin Kang ,  Shu-Lu Chen

IPC分类号： H01L31/0216 ,  H01L31/0224 ,  H04B10/60 ,  H01L31/0232 ,  H01L31/108 ,  H01L31/18 ,  H01L31/107 ,  H01L31/028

CPC分类号： H01L31/02161 ,  G02B6/12004 ,  H01L31/022408 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/03529 ,  H01L31/107 ,  H01L31/1085 ,  H01L31/1868 ,  H01L31/1872 ,  H04B10/60 ,  Y02E10/547 ,  Y02P70/521

摘要： A low voltage photodetector structure including a semiconductor device layer, which may be Ge, is disposed over a substrate semiconductor, which may be Si, for example within a portion of a waveguide extending laterally within a photonic integrated circuit (PIC) chip. In exemplary embodiments where the device layer is formed over an insulator layer, the insulator layer is removed to expose a surface of the semiconductor device layer and a passivation material formed as a replacement for the insulator layer within high field regions. In further embodiments, controlled avalanche gain is achieved by spacing electrodes in a metal-semiconductor-metal (MSM) architecture, or complementary doped regions in a p-i-n architecture, to provide a field strength sufficient for impact ionization over a distance not significantly more than an order of magnitude greater than the distance that a carrier must travel so as to acquire sufficient energy for impact ionization.

摘要翻译： 包括可以是Ge的半导体器件层的低电压光电检测器结构设置在衬底半导体上，衬底半导体可以是Si，例如在光子集成电路（PIC）芯片内横向延伸的波导的一部分内。 在其中器件层形成在绝缘体层上的示例性实施例中，去除绝缘体层以暴露半导体器件层的表面和形成为高场区域内的绝缘体层的替代物的钝化材料。 在另外的实施例中，受控的雪崩增益通过在金属 - 半导体 - 金属（MSM）结构中的电极间隔或引脚结构中的互补掺杂区域间隔来实现，以提供足够的冲击电离的场强，该距离不大于 数量级大于载体必须行进的距离，以获得足够的能量进行冲击电离。

公开(公告)号：US08665385B2

公开(公告)日：2014-03-04

申请号：US13274193

申请日：2011-10-14

申请人： Shu-Lu Chen

发明人： Shu-Lu Chen

IPC分类号： G02F1/1343

CPC分类号： G09G3/3648 ,  G02F1/13306 ,  G02F1/1362 ,  G02F1/1368 ,  G02F2001/133374 ,  G09G2300/0857

摘要： A non-volatile electronic display includes a light valve plate comprising a plurality of liquid crystal cells on a transparent substrate; a plurality of “floating/storage” nodes functioning like non-volatile memories formed on the transparent substrate and corresponding to the liquid crystal cells, and a plurality of word lines and a plurality of bit lines connected to the plurality of non-volatile memories and supplying signal to store charge to at least one non-volatile memory. The charge is retained in the at least one “floating/storage” nodes functioning like non-volatile memory for a predetermined period when no external power is applied to the non-volatile electronic display.

摘要翻译： 非挥发性电子显示器包括在透明基板上包括多个液晶单元的光阀板; 在透明基板上形成并对应于液晶单元的多个“浮动/存储”节点的功能类似于非易失性存储器，以及连接到多个非易失性存储器的多个字线和多个位线， 提供信号以将电荷存储到至少一个非易失性存储器。 当没有外部电力施加到非易失性电子显示器时，电荷保持在至少一个像非易失性存储器一样运行预定时间的“浮动/存储”节点。

公开(公告)号：US08653598B2

公开(公告)日：2014-02-18

申请号：US13226218

申请日：2011-09-06

申请人： Shu-Lu Chen

发明人： Shu-Lu Chen

IPC分类号： H01L27/12 ,  H01L29/76 ,  H01L23/62 ,  H01L27/11 ,  H01L21/70 ,  H01L29/00

CPC分类号： H01L21/823807 ,  H01L21/76254 ,  H01L21/823828 ,  H01L27/0688 ,  H01L29/66621 ,  H01L29/7838 ,  H01L29/78654 ,  H01L2924/0002 ,  Y02P80/30 ,  H01L2924/00

摘要： An electrical switch using a gated resistor structure includes an isolation layer, a doped silicon layer arranged on the isolation layer and having a recessed portion with reduced thickness, the doped silicon layer having a predetermined doping type and a predetermined doping profile; a gate layer arranged corresponding to the recessed portion. The recessed portion in the doped silicon layer has such thickness that a channel defined under the gate can be fully depleted to form a high resistivity region. The recessed channel gated resistor structure can be advantageously used to achieve high interconnect density with low thermal budget for 3D integration.

摘要翻译： 使用门控电阻器结构的电开关包括隔离层，布置在隔离层上的掺杂硅层，并具有厚度减小的凹陷部分，掺杂硅层具有预定的掺杂类型和预定的掺杂分布; 对应于所述凹部布置的栅极层。 掺杂硅层中的凹陷部分具有这样的厚度，使得限定在栅极下方的沟道可以完全耗尽以形成高电阻率区域。 凹陷通道门控电阻器结构可以有利地用于实现具有低热预算的高互连密度以用于3D集成。

公开(公告)号：US20090294869A1

公开(公告)日：2009-12-03

申请号：US12472345

申请日：2009-05-26

申请人： Shu-Lu Chen

发明人： Shu-Lu Chen

IPC分类号： H01L27/092 ,  H01L21/70

CPC分类号： H01L27/1203 ,  G11C11/39 ,  H01L27/092 ,  H01L27/11 ,  Y10T29/41

摘要： A negative differential resistance (NDR) device is designed and a possible compact device implementation is presented. The NDR device includes a voltage blocker and a current blocker and exhibits high peak-to-valley current ratio (PVCR) as well as high switching speed. The corresponding process and design are completely compatible with contemporary Si CMOS technology and area efficient. A single-NDR element SRAM cell prototype with a compact size and high speed is also proposed as its application suitable for embedded memory.

摘要翻译： 设计了负差分电阻（NDR）器件，并提出了可能的紧凑型器件实现。 NDR器件包括电压阻断器和电流阻断器，并且具有高的峰谷电流比（PVCR）以及高切换速度。 相应的工艺和设计与当今的Si CMOS技术和区域高效完全兼容。 还提出具有紧凑尺寸和高速度的单NDR元件SRAM单元原型作为其适用于嵌入式存储器的应用。

公开(公告)号：US20120092575A1

公开(公告)日：2012-04-19

申请号：US13274193

申请日：2011-10-14

申请人： Shu-Lu CHEN

发明人： Shu-Lu CHEN

IPC分类号： G02F1/1343 ,  H01L27/15

CPC分类号： G09G3/3648 ,  G02F1/13306 ,  G02F1/1362 ,  G02F1/1368 ,  G02F2001/133374 ,  G09G2300/0857

摘要： A non-volatile electronic display includes a light valve plate comprising a plurality of liquid crystal cells on a transparent substrate; a plurality of “floating/storage” nodes functioning like non-volatile memories formed on the transparent substrate and corresponding to the liquid crystal cells, and a plurality of word lines and a plurality of bit lines connected to the plurality of non-volatile memories and supplying signal to store charge to at least one non-volatile memory. The charge is retained in the at least one “floating/storage” nodes functioning like non-volatile memory for a predetermined period when no external power is applied to the non-volatile electronic display.

摘要翻译： 非挥发性电子显示器包括在透明基板上包括多个液晶单元的光阀板; 在透明基板上形成并对应于液晶单元的多个“浮动/存储”节点的功能类似于非易失性存储器，以及连接到多个非易失性存储器的多个字线和多个位线， 提供信号以将电荷存储到至少一个非易失性存储器。 当没有外部电力施加到非易失性电子显示器时，电荷保持在至少一个像非易失性存储器一样运行预定时间的“浮动/存储”节点。

公开(公告)号：US07749872B2

公开(公告)日：2010-07-06

申请号：US12392261

申请日：2009-02-25

申请人： James D. Plummer ,  Peter B. Griffin ,  Jia Feng ,  Shu-Lu Chen

发明人： James D. Plummer ,  Peter B. Griffin ,  Jia Feng ,  Shu-Lu Chen

IPC分类号： H01L21/20

CPC分类号： H01L29/66742 ,  B82Y10/00 ,  H01L21/02433 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02667 ,  H01L21/02675 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78684

摘要： Single-crystalline growth is realized using a liquid-phase crystallization approach involving the inhibition of defects typically associated with liquid-phase crystalline growth of lattice mismatched materials. According to one example embodiment, a semiconductor device structure includes a substantially single-crystal region. A liquid-phase material, such as Ge or a semiconductor compound, is crystallized to form the single-crystal region using an approach involving defect inhibition for the promotion of single-crystalline growth. In some instances, this defect inhibition involves the reduction and/or elimination of defects using a relatively small physical opening via which a crystalline growth front propagates. In other instances, this defect inhibition involves causing a change in crystallization front direction relative to a crystallization seed location. The relatively small physical opening and/or the change in crystalline front direction may be implemented, for example, using a material that is substantially unreactive with the liquid-phase material to contain the crystalline growth.

摘要翻译： 使用液相结晶方法实现单晶生长，其涉及通常与晶格失配材料的液相晶体生长相关的缺陷的抑制。 根据一个示例性实施例，半导体器件结构包括基本单晶区域。 使用涉及促进单晶生长的缺陷抑制的方法，使诸如Ge或半导体化合物的液相材料结晶形成单晶区域。 在一些情况下，该缺陷抑制包括使用晶体生长前沿传播的相对小的物理开口来减少和/或消除缺陷。 在其他情况下，该缺陷抑制涉及相对于结晶种子位置导致结晶前沿方向的变化。 可以例如使用与液相材料基本上不反应的材料以包含结晶生长来实现相对较小的物理开口和/或晶体前端方向的变化。