公开(公告)号：US09099492B2

公开(公告)日：2015-08-04

申请号：US13429787

申请日：2012-03-26

Applicant: Kuldeep Amarnath ,  Michael Hargrove ,  Srikanth Samavedam

Inventor： Kuldeep Amarnath ,  Michael Hargrove ,  Srikanth Samavedam

IPC: H01L29/66 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/1033 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/7848

Abstract: Disclosed herein are various methods of forming replacement gate structures with a recessed channel region. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define an initial gate opening having sidewalls and to expose a surface of the substrate and performing an etching process on the exposed surface of the substrate to define a recessed channel in the substrate. The method includes the additional steps of forming a sidewall spacer within the initial gate opening on the sidewalls of the initial gate opening to thereby define a final gate opening and forming a replacement gate structure in the final gate opening.

Abstract translation: 本文公开了形成具有凹陷沟道区域的替换栅极结构的各种方法。 在一个示例中，该方法包括在半导体衬底之上形成牺牲栅极结构，去除牺牲栅极结构，从而限定具有侧壁的初始栅极开口并暴露衬底的表面，并在衬底的暴露表面上执行蚀刻工艺 衬底以在衬底中限定凹陷通道。 该方法包括在初始栅极开口的侧壁上的初始栅极开口内形成侧壁间隔物以由此限定最终栅极开口并在最终栅极开口中形成替换栅极结构的附加步骤。

公开(公告)号：US08598009B2

公开(公告)日：2013-12-03

申请号：US13456633

申请日：2012-04-26

Applicant: Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

Inventor： Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

IPC: H01L21/8222

CPC classification number: H01L29/66636 ,  H01L21/3247 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7848

Abstract: A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.

Abstract translation: 低能量表面通过栅极堆叠的每一侧的沟槽表面的高温退火形成。 半导体层的材料在高温退火期间回流，使得低能表面是与半导体层的表面法线成非正交角的结晶表面。 在半导体层上选择性地生长晶格失配的半导体材料以填充沟槽，从而在晶体管的源极和漏极区域中形成嵌入的晶格失配的半导体材料部分。 嵌入的晶格不匹配的半导体材料部分可以原位掺杂而不增加穿通。 或者，可以采用固有选择性外延和离子注入的组合来形成深的源极和漏极区域。

公开(公告)号：US08222673B2

公开(公告)日：2012-07-17

申请号：US12795683

申请日：2010-06-08

Applicant: Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

Inventor： Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

IPC: H01L21/02

CPC classification number: H01L29/66636 ,  H01L21/3247 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7848

Abstract: A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.

Abstract translation: 低能量表面通过栅极堆叠的每一侧的沟槽表面的高温退火形成。 半导体层的材料在高温退火期间回流，使得低能表面是与半导体层的表面法线成非正交角的结晶表面。 在半导体层上选择性地生长晶格失配的半导体材料以填充沟槽，从而在晶体管的源极和漏极区域中形成嵌入的晶格失配的半导体材料部分。 嵌入的晶格不匹配的半导体材料部分可以原位掺杂而不增加穿通。 或者，可以采用固有选择性外延和离子注入的组合来形成深的源极和漏极区域。

公开(公告)号：US20130344669A1

公开(公告)日：2013-12-26

申请号：US13529898

申请日：2012-06-21

Applicant: Jia Feng ,  Kuldeep Amarnath ,  Kevin J. Yang

Inventor： Jia Feng ,  Kuldeep Amarnath ,  Kevin J. Yang

IPC: H01L21/336

CPC classification number: H01L29/66545 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/456 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/7835 ,  H01L29/7843

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including a first region of a first doping type, a second region of the first doping type spaced from the first region, a drift region of the first doping type positioned between the first region and the second region, and regions of the opposite doping type. A mask covering both the drift region and the regions of the opposite doping type is formed. Then, a source/drain ion implantation is performed into the first region and the second region. The mask prevents the drift region and the regions of the opposite doping type from receiving the source/drain ion implantation.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括：提供包括第一掺杂类型的第一区域，与第一区域间隔开的第一掺杂类型的第二区域的半导体衬底，位于第一掺杂类型的第一掺杂类型的漂移区域 第一区域和第二区域以及相反掺杂类型的区域。 形成覆盖漂移区域和相反掺杂类型的区域的掩模。 然后，对第一区域和第二区域进行源/漏离子注入。 掩模防止漂移区域和相反掺杂类型的区域接收源极/漏极离子注入。

公开(公告)号：US20120208337A1

公开(公告)日：2012-08-16

申请号：US13456633

申请日：2012-04-26

Applicant: Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

Inventor： Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/3247 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7848

Abstract: A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.

Abstract translation: 低能量表面通过栅极堆叠的每一侧的沟槽表面的高温退火形成。 半导体层的材料在高温退火期间回流，使得低能表面是与半导体层的表面法线成非正交角的结晶表面。 在半导体层上选择性地生长晶格失配的半导体材料以填充沟槽，从而在晶体管的源极和漏极区域中形成嵌入的晶格失配的半导体材料部分。 嵌入的晶格不匹配的半导体材料部分可以原位掺杂而不增加穿通。 或者，可以采用固有选择性外延和离子注入的组合来形成深的源极和漏极区域。

公开(公告)号：US08361894B1

公开(公告)日：2013-01-29

申请号：US13439185

申请日：2012-04-04

Applicant: Michael J. Hargrove ,  Kuldeep Amarnath

Inventor： Michael J. Hargrove ,  Kuldeep Amarnath

IPC: H01L21/425

CPC classification number: H01L27/1211 ,  H01L21/845

Abstract: One illustrative method disclosed herein includes forming first and second FinFET devices in and above a first region and a second region of a semiconducting substrate, respectively, performing a first ion implantation process through a patterned mask layer to implant nitrogen into the second region, removing the patterned mask layer, performing a second ion implantation process to implant oxygen atoms into both the first and second regions, performing a heating process to form a layer of insulating material at least in the first region and performing at least one etching process to define at least one first fin in the first region and to define at least one second fin in the second region, the second fin being taller than the first fin.

Abstract translation: 本文公开的一种说明性方法包括分别在半导体衬底的第一区域和第二区域中和上方形成第一和第二FinFET器件，通过图案化掩模层进行第一离子注入工艺以将氮植入第二区域， 图案化掩模层，执行第二离子注入工艺以将氧原子注入到第一和第二区域中，执行加热过程以至少在第一区域中形成绝缘材料层，并执行至少一个蚀刻工艺以至少限定 在所述第一区域中的一个第一鳍片并且在所述第二区域中限定至少一个第二鳍片，所述第二鳍片比所述第一鳍片高。

公开(公告)号：US20110298008A1

公开(公告)日：2011-12-08

申请号：US12795683

申请日：2010-06-08

Applicant: Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

Inventor： Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/3247 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7848

Abstract: A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.

Abstract translation: 低能量表面通过栅极堆叠的每一侧的沟槽表面的高温退火形成。 半导体层的材料在高温退火期间回流，使得低能表面是与半导体层的表面法线成非正交角的结晶表面。 在半导体层上选择性地生长晶格失配的半导体材料以填充沟槽，从而在晶体管的源极和漏极区域中形成嵌入的晶格失配的半导体材料部分。 嵌入的晶格不匹配的半导体材料部分可以原位掺杂而不增加穿通。 或者，可以采用固有选择性外延和离子注入的组合来形成深的源极和漏极区域。

公开(公告)号：US08940608B2

公开(公告)日：2015-01-27

申请号：US13529898

申请日：2012-06-21

Applicant: Jia Feng ,  Kuldeep Amarnath ,  Kevin J. Yang

Inventor： Jia Feng ,  Kuldeep Amarnath ,  Kevin J. Yang

IPC: H01L21/336

CPC classification number: H01L29/66545 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/456 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/7835 ,  H01L29/7843

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including a first region of a first doping type, a second region of the first doping type spaced from the first region, a drift region of the first doping type positioned between the first region and the second region, and regions of the opposite doping type. A mask covering both the drift region and the regions of the opposite doping type is formed. Then, a source/drain ion implantation is performed into the first region and the second region. The mask prevents the drift region and the regions of the opposite doping type from receiving the source/drain ion implantation.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括：提供包括第一掺杂类型的第一区域，与第一区域间隔开的第一掺杂类型的第二区域的半导体衬底，位于第一掺杂类型的第一掺杂类型的漂移区域 第一区域和第二区域以及相反掺杂类型的区域。 形成覆盖漂移区域和相反掺杂类型的区域的掩模。 然后，对第一区域和第二区域进行源/漏离子注入。 掩模防止漂移区域和相反掺杂类型的区域接收源极/漏极离子注入。

公开(公告)号：US20190258911A1

公开(公告)日：2019-08-22

申请号：US16205078

申请日：2018-11-29

Applicant: Kuldeep AMARNATH ,  Ashutosh DHODAPKAR

Inventor： Kuldeep AMARNATH ,  Ashutosh DHODAPKAR

IPC: G06K19/077 ,  G06K19/06 ,  G06K7/08

Abstract: A method for designing and constructing a thin programmable dynamic credential card is disclosed. The thin programmable dynamic credential card may comprise nine different layers carefully constructed to house a battery, a processor, a wireless communication system, a solenoid coil, a graphical display, input buttons, and other electrical components all within the thin form factor of a credit card.

公开(公告)号：US20160188916A1

公开(公告)日：2016-06-30

申请号：US14922771

申请日：2015-10-26

Applicant: Kuldeep Amarnath ,  Ashutosh Dhodapkar

Inventor： Kuldeep Amarnath ,  Ashutosh Dhodapkar

IPC: G06K7/08

CPC classification number: G06K19/07722 ,  G06K7/087 ,  G06K19/06206 ,  G06K19/07745

Abstract: Conventional magnetic stripe cards are encoded with static magnetic patterns. To act like many different magnetic stripe cards, a programmable dynamic magnetic stripe card disclosed. The programmable dynamic magnetic stripe card includes a solenoid coil for generating a magnetic field and solenoid coil driver circuitry for driving the solenoid coil to generate a magnetic field. To improve the quality of the magnetic field generated, a biasing magnet is placed adjacent to the solenoid coil.

Abstract translation: 常规磁条卡用静态磁图案编码。 像许多不同的磁条卡一样，公开了一种可编程动态磁条卡。 可编程动态磁条卡包括用于产生磁场的螺线管线圈和用于驱动螺线管线圈以产生磁场的螺线管线圈驱动器电路。 为了提高所产生的磁场的质量，偏置磁体被放置成与电磁线圈相邻。