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公开(公告)号：US08520458B2
公开(公告)日：2013-08-27
申请号：US13530889
申请日：2012-06-22
CPC分类号： G11C7/12 , G11C7/22 , G11C13/0004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0076
摘要： A phase change memory (PCM) cycle timer and associated method are disclosed. A system includes at least one reference phase change element (PCE). The system also includes a circuit that performs a write operation on the at least one reference PCE and substantially immediately thereafter continuously senses and returns a value of a resistance of the at least one reference PCE throughout a settling time of the at least one reference PCE.
摘要翻译： 公开了一种相变存储器（PCM）周期定时器及相关方法。 系统包括至少一个参考相变元件（PCE）。 该系统还包括对至少一个参考PCE执行写操作并且基本上立即在该连续感测并且在至少一个参考PCE的整个建立时间内返回至少一个参考PCE的电阻值的电路。
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公开(公告)号：US20080084760A1
公开(公告)日：2008-04-10
申请号：US11538945
申请日：2006-10-05
IPC分类号： G11C11/34
CPC分类号： G11C7/067 , G11C7/06 , G11C13/00 , G11C13/004 , G11C2213/79
摘要： The embodiments of the invention provide an apparatus, method, etc. for an efficient circuit and method to measure resistance. A sense line driver for an integrated circuit memory is provided, including a sense node that receives an experiment signal from an experiment structure. An output device is connected to the sense node, wherein the output device amplifies the experiment signal. Further, a voltage divider is connected to the sense node, wherein the voltage divider includes a first device and a second device. A sensing range is controlled by an operating width/resistance range and/or an adjust signal of the second device. The adjust signal changes a gate to source voltage of the second device and holds a constant voltage over multiple sensing instances. The sensing range is different for each of the sensing instances due to a change in the operating width of the second device.
摘要翻译： 本发明的实施例提供了一种用于测量电阻的有效电路和方法的装置，方法等。 提供了一种用于集成电路存储器的感测线驱动器，包括从实验结构接收实验信号的感测节点。 输出设备连接到感测节点，其中输出设备放大实验信号。 此外，分压器连接到感测节点，其中分压器包括第一器件和第二器件。 感测范围由第二设备的操作宽度/电阻范围和/或调整信号控制。 调整信号改变第二器件的栅极到源极电压，并且在多个感测实例上保持恒定的电压。 由于第二设备的操作宽度的变化，感测范围对于每个感测实例是不同的。
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公开(公告)号：US20120266115A1
公开(公告)日：2012-10-18
申请号：US13530889
申请日：2012-06-22
IPC分类号： G06F17/50
CPC分类号： G11C7/12 , G11C7/22 , G11C13/0004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0076
摘要： A phase change memory (PCM) cycle timer and associated method are disclosed. A system includes at least one reference phase change element (PCE). The system also includes a circuit that performs a write operation on the at least one reference PCE and substantially immediately thereafter continuously senses and returns a value of a resistance of the at least one reference PCE throughout a settling time of the at least one reference PCE.
摘要翻译： 公开了一种相变存储器（PCM）周期定时器及相关方法。 系统包括至少一个参考相变元件（PCE）。 该系统还包括对至少一个参考PCE执行写操作并且基本上立即在该连续感测并且在至少一个参考PCE的整个建立时间内返回至少一个参考PCE的电阻值的电路。
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公开(公告)号：US07613047B2
公开(公告)日：2009-11-03
申请号：US11538945
申请日：2006-10-05
IPC分类号： G11C16/06
CPC分类号： G11C7/067 , G11C7/06 , G11C13/00 , G11C13/004 , G11C2213/79
摘要： The embodiments of the invention provide an apparatus, method, etc. for an efficient circuit and method to measure resistance. A sense line driver for an integrated circuit memory is provided, including a sense node that receives an experiment signal from an experiment structure. An output device is connected to the sense node, wherein the output device amplifies the experiment signal. Further, a voltage divider is connected to the sense node, wherein the voltage divider includes a first device and a second device. A sensing range is controlled by an operating width/resistance range and/or an adjust signal of the second device. The adjust signal changes a gate to source voltage of the second device and holds a constant voltage over multiple sensing instances. The sensing range is different for each of the sensing instances due to a change in the operating width of the second device.
摘要翻译： 本发明的实施例提供了一种用于测量电阻的有效电路和方法的装置，方法等。 提供了一种用于集成电路存储器的感测线驱动器，包括从实验结构接收实验信号的感测节点。 输出设备连接到感测节点，其中输出设备放大实验信号。 此外，分压器连接到感测节点，其中分压器包括第一器件和第二器件。 感测范围由第二设备的操作宽度/电阻范围和/或调整信号控制。 调整信号改变第二器件的栅极到源极电压，并且在多个感测实例上保持恒定的电压。 由于第二设备的操作宽度的变化，感测范围对于每个感测实例是不同的。
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公开(公告)号：US07016251B2
公开(公告)日：2006-03-21
申请号：US10710707
申请日：2004-07-29
申请人： John A. Gabric , Harold Pilo
发明人： John A. Gabric , Harold Pilo
IPC分类号： G11C7/00
CPC分类号： G11C7/20 , G11C7/12 , G11C11/413
摘要： A method for initializing a static random access memory (SRAM) device during power-up includes clamping one of a pair of bitlines of the SRAM device to a logic low potential while allowing the other of the pair of bitlines to be coupled to a charging logic high potential. An SRAM storage cell within the SRAM device is forced to a stable state by selectively allowing a wordline potential of a wordline associated with the SRAM storage cell to follow the charging logic high potential, thereby coupling the SRAM storage cell to the pair of bitlines.
摘要翻译： 用于在上电期间初始化静态随机存取存储器（SRAM）器件的方法包括将SRAM器件的一对位线中的一个钳位到逻辑低电位，同时允许该对位线中的另一个耦合到充电逻辑 高潜力 SRAM器件中的SRAM存储单元通过选择性地允许与SRAM存储单元相关联的字线的字线电位跟随充电逻辑高电位而强制进入稳定状态，从而将SRAM存储单元耦合到该对位线。
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公开(公告)号：US5019772A
公开(公告)日：1991-05-28
申请号：US355589
申请日：1989-05-23
IPC分类号： G01R31/28 , G01R31/317 , H01L21/66
CPC分类号： G01R31/31701
摘要： A test selection system is provided which includes a semiconductor substrate having a pin connected thereto and an integrated circuit disposed on the substrate and connected to the pin having an operating voltage within a given voltage range. A latch conditioning circuit having an input responsive to a voltage of a given magnitude has an output connected to a latch, and a voltage control circuit operable at a voltage without the given voltage range selectively applies a control voltage of the given magnitude to the input of the latch conditioning circuit. A voltage without the given voltage range is applied to the pin during a first interval of time to produce the control voltage for establishing a test mode and a voltage within the given voltage range is applied to the pin during a second interval of time to establish a normal operating mode for the integrated circuit.
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公开(公告)号：US08233345B2
公开(公告)日：2012-07-31
申请号：US12877628
申请日：2010-09-08
IPC分类号： G11C7/02
CPC分类号： G11C7/12 , G11C7/22 , G11C13/0004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0076
摘要： A phase change memory (PCM) cycle timer and associated method are disclosed. A system includes at least one reference phase change element (PCE). The system also includes a circuit that performs a write operation on the at least one reference PCE and substantially immediately thereafter continuously senses and returns a value of a resistance of the at least one reference PCE throughout a settling time of the at least one reference PCE.
摘要翻译： 公开了一种相变存储器（PCM）周期定时器及相关方法。 系统包括至少一个参考相变元件（PCE）。 该系统还包括对至少一个参考PCE执行写操作并且基本上立即在该连续感测并且在至少一个参考PCE的整个建立时间内返回至少一个参考PCE的电阻值的电路。
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公开(公告)号：US20120057401A1
公开(公告)日：2012-03-08
申请号：US12877628
申请日：2010-09-08
IPC分类号： G11C11/00
CPC分类号： G11C7/12 , G11C7/22 , G11C13/0004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0076
摘要： A phase change memory (PCM) cycle timer and associated method are disclosed. A system includes at least one reference phase change element (PCE). The system also includes a circuit that performs a write operation on the at least one reference PCE and substantially immediately thereafter continuously senses and returns a value of a resistance of the at least one reference PCE throughout a settling time of the at least one reference PCE.
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9.发明授权Integrated circuit module having reduced impedance and method of providing the same 失效具有减小阻抗的集成电路模块及其提供方法公开(公告)号：US06177833B1
公开(公告)日：2001-01-23
申请号：US09303293
申请日：1999-04-30
IPC分类号： H01L2500
CPC分类号： H01L23/66 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated semiconductor module of reduced impedance and method utilizing a given chip architecture of the type having a memory circuit and a plurality of off-chip drivers and their I/O pads, the module being constructed in a configuration for operation of said memory circuit with less than the number of available drivers such that there are a number of excess drivers and output pads not used for driver operations, and one or more of these excess drivers and their pads are connected to the power terminals of the chip to provide one or more power paths through these drivers and their associated pads in parallel with the power paths of the operational drivers, and the method includes connecting the excess drivers and their output pads to the power terminals of the chip during its fabrication in a manner to provide additional power paths.
摘要翻译： 一种具有减小阻抗的集成半导体模块和利用具有存储器电路和多个片外驱动器及其I / O焊盘的类型的给定芯片架构的模块，该模块被构造成用于操作所述存储器电路的配置， 小于可用驱动器的数量，使得存在多个驱动器和输出焊盘不用于驱动器操作的数量，并且这些过量驱动器及其焊盘中的一个或多个连接到芯片的电源端子以提供一个或多个 通过这些驱动器的电源路径及其相关联的焊盘与操作驱动器的电源路径并联，并且该方法包括在其制造过程中将多余的驱动器及其输出焊盘连接到芯片的电源端子，以提供额外的电源路径 。
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公开(公告)号：US4599520A
公开(公告)日：1986-07-08
申请号：US575612
申请日：1984-01-31
申请人： John A. Gabric , Edward F. O'Neil
发明人： John A. Gabric , Edward F. O'Neil
IPC分类号： G06F1/04 , G11C11/407 , H03K5/02 , H03K17/06 , H03K19/017 , H03K19/096 , H03K5/135 , H03K17/10 , H03K17/687
CPC分类号： H03K19/01735
摘要： An FET double boosted clock driver for producing a clock signal having an amplitude greater than the drain supply voltage. The clock output of a second clock driver is capacitively coupled to the clock output of a first clock driver. The second clock driver boosts the voltage on the source of an enhancement mode (output) FET of the first clock driver. The output FET has its gate connected to a bootstrapped node and its drain connected to a drain voltage source (VDD). A depletion mode FET forms a feedback path between the source of the output node FET and the bootstrapped node. When the bootstrapped node is bootstrapped to VDD+VT, the output FET precharges the clock output to VDD. When the potential of the clock output approaches VDD, the depletion mode FET discharges the bootstrapped node to an input clock. Thus, the potential of the gate of the output FET is clamped to the drain supply voltage when the output is subsequently boosted by the capacitively coupled second clock driver, without adversely effecting the timing and the precharging of the enhancement mode output FET.
摘要翻译： FET双升压时钟驱动器，用于产生幅度大于漏极电源电压的时钟信号。 第二时钟驱动器的时钟输出电容耦合到第一时钟驱动器的时钟输出。 第二个时钟驱动器提升了第一个时钟驱动器的增强模式（输出）FET源极上的电压。 输出FET的栅极连接到自举节点，其漏极连接到漏极电压源（VDD）。 耗尽型FET在输出节点FET的源和引导节点之间形成反馈路径。 当自举节点自举到VDD + VT时，输出FET将时钟输出预充电至VDD。 当时钟输出的电位接近VDD时，耗尽型FET将自举节点放电到输入时钟。 因此，当输出随后由电容耦合的第二时钟驱动器升压时，输出FET的栅极的电位被钳位到漏极电源电压，而不会不利地影响增强模式输出FET的定时和预充电。
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