公开(公告)号：US6093335A

公开(公告)日：2000-07-25

申请号：US974210

申请日：1997-11-20

申请人： Ashwinkumar C. Bhatt ,  John Christopher Camp ,  Subahu Dhirubhai Desai ,  Voya Rista Markovich ,  Michael Wozniak

发明人： Ashwinkumar C. Bhatt ,  John Christopher Camp ,  Subahu Dhirubhai Desai ,  Voya Rista Markovich ,  Michael Wozniak

IPC分类号： B24B7/06 ,  B24B37/04 ,  B24B41/047 ,  C23F1/08 ,  H05K3/06 ,  H05K3/26 ,  B44C1/22

CPC分类号： B24B7/06 ,  B24B37/04 ,  B24B41/047 ,  C23F1/08 ,  H05K3/068 ,  H05K3/26 ,  H05K2203/025 ,  H05K2203/0346 ,  H05K2203/0353 ,  H05K2203/1509

摘要： A method for planarizing an exposed metal surface on a substrate is provided in which surface irregularities are eliminated. A photoresist layer is first removed from the substrate. Then a conformal planarizing head is placed in contact with the metal surface while chemical etchant essentially free of abrasives is supplied to an interface between the metal substrate and the planarizing head. The surface is then planarized until it is free of irregularties.

摘要翻译： 提供了在基板上平坦化露出的金属表面的方法，其中消除了表面凹凸。 首先从基底去除光致抗蚀剂层。 然后将保形平面化头与金属表面接触，同时基本上没有磨料的化学蚀刻剂被提供给金属基底和平坦化头之间的界面。 然后将表面平坦化，直到其没有不规则。

公开(公告)号：US06544584B1

公开(公告)日：2003-04-08

申请号：US08813765

申请日：1997-03-07

申请人： Edward Lee Arrington ,  John Christopher Camp ,  Robert Jeffrey Day ,  Edmond Otto Fey ,  Curtis Michael Gunther ,  Thomas Richard Miller

发明人： Edward Lee Arrington ,  John Christopher Camp ,  Robert Jeffrey Day ,  Edmond Otto Fey ,  Curtis Michael Gunther ,  Thomas Richard Miller

IPC分类号： B05D512

CPC分类号： H05K3/26 ,  H05K3/184 ,  H05K2201/0761 ,  H05K2203/0796 ,  Y10S428/901 ,  Y10T428/12396 ,  Y10T428/12715 ,  Y10T428/12861 ,  Y10T428/12868 ,  Y10T428/24917 ,  Y10T428/31678

摘要： A process for removal of undesirable conductive material (e.g., catalyst material and seeped circuit material) on a circuitized substrate and the resultant circuitized substrates disclosed. Such process and resultant circuit effectively address the electrical shorting problems caused by nonremoval of the residual catalyst material and circuit material which has seeped under the residual catalyst material. The process includes the steps of: a) providing a catalyst layer (e.g., palladium and tin) having circuit pattern (e.g., copper) thereon; b) pretreating the catalyst layer and the circuit pattern (e.g., with a cyanide dip) for removal of undesirable portions of each which cause electrical leakage between circuit lines of the circuit pattern; c) oxidizing the catalyst layer and the circuit pattern (e.g., with chlorite, permanganate, hydrogen peroxide, or air at a temperature elevated above ambient conditions); and d) removing the undesirable portions of the catalyst layer and the undesirable portions of the circuit pattern (e.g., with a cyanide submersion). The resultant circuitized substrate includes a circuit pattern on a catalyst layer wherein undesirable portions of the catalyst layer and circuit pattern are completely removed between the circuit features of the circuit pattern so that electrical leakage between the circuit features does not occur.

摘要翻译： 用于去除电路化基板上的不期望的导电材料（例如催化剂材料和渗出的电路材料）的方法以及公开的所得的电路化基板。 这种工艺和结果电路有效地解决了残余催化剂材料和残余催化剂材料下渗出的电路材料的非破坏所引起的电短路问题。 该方法包括以下步骤：a）在其上提供具有电路图案（例如铜）的催化剂层（例如钯和锡） b）预处理催化剂层和电路图案（例如，用氰化物浸渍），以除去在电路图案的电路线之间引起漏电的各部分的不希望的部分; c）氧化催化剂层和电路图案（例如，在高于环境条件的温度下使用亚氯酸盐，高锰酸盐，过氧化氢或空气）; 以及d）去除催化剂层的不期望的部分和电路图案的不希望的部分（例如，氰化物浸没）。 所得到的电路化衬底包括在催化剂层上的电路图案，其中在电路图案的电路特征之间催化剂层和电路图案的不期望部分被完全去除，使得电路特征之间的电泄漏不会发生。

公开(公告)号：US6063481A

公开(公告)日：2000-05-16

申请号：US36065

申请日：1998-03-06

申请人： Edward Lee Arrington ,  John Christopher Camp ,  Robert Jeffrey Day ,  Edmond Otto Fey ,  Curtis Michael Gunther ,  Thomas Richard Miller

发明人： Edward Lee Arrington ,  John Christopher Camp ,  Robert Jeffrey Day ,  Edmond Otto Fey ,  Curtis Michael Gunther ,  Thomas Richard Miller

IPC分类号： H05K3/18 ,  H05K3/26 ,  B32B3/00 ,  B32B15/04

CPC分类号： H05K3/26 ,  H05K3/184 ,  H05K2201/0761 ,  H05K2203/0796 ,  Y10S428/901 ,  Y10T428/12396 ,  Y10T428/12715 ,  Y10T428/12861 ,  Y10T428/12868 ,  Y10T428/24917

摘要： A process for removal of undesirable conductive material (e.g., catalyst material and seeped circuit material) on a circuitized substrate and the resultant circuitized substrates disclosed. Such process and resultant circuit effectively address the electrical shorting problems caused by nonremoval of the residual catalyst material and circuit material which has seeped under the residual catalyst material. The process includes the steps of: a) providing a catalyst layer (e.g., palladium and tin) having circuit pattern (e.g., copper) thereon; b) pretreating the catalyst layer and the circuit pattern (e.g., with a cyanide dip) for removal of undesirable portions of each which cause electrical leakage between circuit lines of the circuit pattern; c) oxidizing the catalyst layer and the circuit pattern (e.g., with chlorite, permanganate, hydrogen peroxide, or air at a temperature elevated above ambient conditions); and d) removing the undesirable portions of the catalyst layer and the undesirable portions of the circuit pattern (e.g., with a cyanide submersion). The resultant circuitized substrate includes a circuit pattern on a catalyst layer wherein undesirable portions of the catalyst layer and circuit pattern are completely removed between the circuit features of the circuit pattern so that electrical leakage between the circuit features does not occur.

摘要翻译： 用于去除电路化基板上的不期望的导电材料（例如催化剂材料和渗出的电路材料）的方法以及公开的所得的电路化基板。 这种工艺和结果电路有效地解决了残余催化剂材料和残余催化剂材料下渗出的电路材料的非破坏所引起的电短路问题。 该方法包括以下步骤：a）在其上提供具有电路图案（例如铜）的催化剂层（例如钯和锡） b）预处理催化剂层和电路图案（例如，用氰化物浸渍），以除去在电路图案的电路线之间引起漏电的各部分的不希望的部分; c）氧化催化剂层和电路图案（例如，在高于环境条件的温度下使用亚氯酸盐，高锰酸盐，过氧化氢或空气）; 以及d）去除催化剂层的不期望的部分和电路图案的不希望的部分（例如，氰化物浸没）。 所得到的电路化衬底包括在催化剂层上的电路图案，其中在电路图案的电路特征之间催化剂层和电路图案的不期望部分被完全去除，使得电路特征之间的电泄漏不会发生。