公开(公告)号：US20230200032A1

公开(公告)日：2023-06-22

申请号：US18166551

申请日：2023-02-09

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shota HAYASHI ,  Nobuaki OGAWA ,  Yuki ASANO ,  Takanori UEJIMA ,  Hiromichi KITAJIMA ,  Takahiro EGUCHI

IPC: H05K9/00 ,  H01L25/065 ,  H01L25/16 ,  H01L23/552 ,  H01L21/56 ,  H05K3/28 ,  H05K1/18

CPC classification number: H05K9/0022 ,  H01L21/56 ,  H01L23/552 ,  H01L25/165 ,  H01L25/0655 ,  H05K1/181 ,  H05K3/284 ,  H05K9/0039 ,  H05K2201/1003 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/10371 ,  H05K2203/025 ,  H05K2203/1316

Abstract: A metal member includes a plate-shaped portion provided on an upper main surface of a substrate, and includes a front main surface and a back main surface arranged in a front-back direction when viewed in an up-down direction. A first electronic component is mounted on the upper main surface of the substrate and is disposed in front of the metal member. A second electronic component is mounted on the upper main surface of the substrate and is disposed behind the metal member. A sealing resin layer is provided on the upper main surface of the substrate and covers the metal member and the one or more electronic components. The plate-shaped portion is provided with one or more upper notches extending downward from the upper side. The metal member further includes one or more foot portions extending forward or backward from the lower side.

公开(公告)号：US20180359886A1

公开(公告)日：2018-12-13

申请号：US16046243

申请日：2018-07-26

Applicant: BRIDGE SEMICONDUCTOR CORP.

Inventor： Charles W. C. LIN ,  Chia-Chung WANG

IPC: H05K13/00 ,  H05K13/04 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498

CPC classification number: H05K13/00 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/16227 ,  H01L2224/18 ,  H05K1/0204 ,  H05K13/0469 ,  H05K13/0486 ,  H05K2201/0187 ,  H05K2201/10106 ,  H05K2203/025 ,  H05K2203/063

Abstract: A method of making an interconnect substrate mainly includes steps of: providing metal posts around a stress modulator, providing a molding compound to bind the stress modulator and the metal posts, providing a crack inhibiting layer on the stress modulator and the molding compound and interfaces between the stress modulator and the molding compound, and depositing metal conductors on the crack inhibiting layer and electrically connected to the metal posts. The metal conductors have interconnect pads superimposed over the stress modulator so that bumps for device connection can be mounted at the area covered by the stress modulator, thereby avoiding cracking of the bumps.

公开(公告)号：US20180332711A1

公开(公告)日：2018-11-15

申请号：US15768190

申请日：2016-09-30

Applicant: PLASMA INNOVATIONS GMBH ,  LPKF LASER & ELECTRONICS AG

Inventor： Michael BISGES ,  Roman OSTHOLT ,  Bernd RÖSENER ,  Daniel DUNKER

IPC: H05K3/10 ,  C23C24/10 ,  H05K3/14 ,  H05K3/18

CPC classification number: H05K3/102 ,  C23C24/106 ,  H05K3/02 ,  H05K3/14 ,  H05K3/182 ,  H05K2203/025 ,  H05K2203/0522 ,  H05K2203/081 ,  H05K2203/088 ,  H05K2203/095 ,  H05K2203/107 ,  H05K2203/1344

Abstract: A method for creating patterned coatings on a molded article includes providing a molded article which has a surface comprising a first area and a second area, at least one surface property in the first area of the surface being different from that in the second area, applying a coating covering at least the first area and the second area to the surface of the molded article, the adhesion of said coating being greater in the first area than in the second area because of the at least one different surface property, and partially removing the coating by means of a removal process which is applied to the entire coating at a constant removal power that is determined such that the entire coating is removed in the second area while the coating remains in place on an entire surface of the first area.

公开(公告)号：US10017133B2

公开(公告)日：2018-07-10

申请号：US15355149

申请日：2016-11-18

Applicant: YAZAKI CORPORATION

Inventor： Mitsunori Tsunoda ,  Gaku Ito ,  Tomoaki Sasaki ,  Shuji Kimura ,  Taku Furuta ,  Shoichi Nomura

IPC: B60R16/02 ,  H05K3/26 ,  H05K1/02 ,  H05K1/18 ,  H05K3/12 ,  H05K3/04 ,  H05K3/24

CPC classification number: B60R16/02 ,  B60R16/0215 ,  H05K1/0265 ,  H05K1/0284 ,  H05K1/181 ,  H05K3/043 ,  H05K3/045 ,  H05K3/125 ,  H05K3/247 ,  H05K3/26 ,  H05K2201/0338 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2201/09036 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/10053 ,  H05K2201/10272 ,  H05K2203/025 ,  H05K2203/0353 ,  H05K2203/0545

Abstract: An instrument panel as a vehicular panel includes a panel body on a surface side of which key tops are installed, a printed wiring section arranged on the surface side of the panel body, and an insulation outer layer arranged on the surface side of the panel body so as to cover the printed wiring section.

公开(公告)号：US09980364B2

公开(公告)日：2018-05-22

申请号：US15077211

申请日：2016-03-22

Applicant: YAZAKI CORPORATION

Inventor： Akira Harao ,  Mototatsu Matsunaga ,  Yasuhiro Sugiura ,  Minoru Kubota

IPC: H05K1/00 ,  H05K1/02 ,  H01R12/72 ,  H05K3/36 ,  H05K1/11 ,  H05K3/10 ,  H01L23/498 ,  H05K7/10 ,  H05K1/05 ,  H05K3/20 ,  H05K3/34 ,  H05K1/14

CPC classification number: H05K1/0204 ,  H01L23/49861 ,  H01L2224/05571 ,  H01L2224/48091 ,  H01L2225/1094 ,  H01R12/728 ,  H05K1/0203 ,  H05K1/05 ,  H05K1/056 ,  H05K1/11 ,  H05K1/14 ,  H05K3/10 ,  H05K3/202 ,  H05K3/3447 ,  H05K3/368 ,  H05K7/1046 ,  H05K2201/09009 ,  H05K2201/09063 ,  H05K2201/10757 ,  H05K2201/10787 ,  H05K2203/025 ,  Y10T29/49147 ,  Y10T29/49155

Abstract: Disclosed is wiring substrate, the wiring substrate including a substrate having a high thermal conductive layer, in which at least one of a front surface and a rear surface of the substrate is a mounting surface for a variety of components; a window section formed in the substrate; and a connection terminal extended from an inside surface portion of the window section and bending in a direction perpendicular to a surface of the substrate.

公开(公告)号：US09949376B2

公开(公告)日：2018-04-17

申请号：US14563778

申请日：2014-12-08

Applicant: Second Sight Medical Products, Inc.

Inventor： Robert J Greenberg ,  Neil H Talbot ,  James S Little

IPC: A61N1/375 ,  A61N1/05 ,  A61N1/36 ,  A61N1/372 ,  H05K3/28 ,  H05K1/11 ,  H05K1/14 ,  A61B5/00 ,  A61B5/0478 ,  H05K1/18 ,  H01L23/055 ,  H05K1/02 ,  H05K1/03 ,  H05K1/09 ,  H05K3/00 ,  H05K3/32 ,  H05K3/36 ,  H05K3/40

CPC classification number: H05K3/282 ,  A61B5/0006 ,  A61B5/0478 ,  A61B5/4836 ,  A61B5/6868 ,  A61B2562/0209 ,  A61B2562/046 ,  A61B2562/125 ,  A61N1/0529 ,  A61N1/0531 ,  A61N1/0534 ,  A61N1/3606 ,  A61N1/36071 ,  A61N1/36082 ,  A61N1/36139 ,  A61N1/375 ,  A61N1/3752 ,  A61N1/3754 ,  H01L23/055 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48465 ,  H05K1/02 ,  H05K1/0271 ,  H05K1/028 ,  H05K1/0281 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/11 ,  H05K1/111 ,  H05K1/145 ,  H05K1/147 ,  H05K1/189 ,  H05K3/0044 ,  H05K3/005 ,  H05K3/0058 ,  H05K3/28 ,  H05K3/321 ,  H05K3/363 ,  H05K3/4015 ,  H05K3/4061 ,  H05K2201/0245 ,  H05K2201/053 ,  H05K2201/055 ,  H05K2201/09063 ,  H05K2201/09145 ,  H05K2201/09163 ,  H05K2201/097 ,  H05K2201/09981 ,  H05K2201/10303 ,  H05K2201/10318 ,  H05K2201/10674 ,  H05K2201/10795 ,  H05K2201/10931 ,  H05K2201/2009 ,  H05K2203/0195 ,  H05K2203/025 ,  H05K2203/0278 ,  H05K2203/0307 ,  H05K2203/068 ,  H05K2203/082 ,  H05K2203/1322 ,  H05K2203/1327 ,  H05K2203/1394 ,  H05K2203/1461 ,  H05K2203/1476 ,  H05K2203/162 ,  H05K2203/304 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The present invention consists of an implantable device with at least one package that houses electronics that sends and receives data or signals, and optionally power, from an external system through at least one coil attached to at least one package and processes the data, including recordings of neural activity, and delivers electrical pulses to neural tissue through at least one array of multiple electrodes that are attached to the at least one package. The device is adapted to electrocorticographic (ECoG) and local field potential (LFP) signals. A brain stimulator, preferably a deep brain stimulator, stimulates the brain in response to neural recordings in a closed feedback loop. The device is advantageous in providing neuromodulation therapies for neurological disorders such as chronic pain, post traumatic stress disorder (PTSD), major depression, or similar disorders. The invention and components thereof are intended to be installed in the head, or on or in the cranium or on the dura, or on or in the brain.

公开(公告)号：US09927349B2

公开(公告)日：2018-03-27

申请号：US15379319

申请日：2016-12-14

Applicant: CANON KABUSHIKI KAISHA

Inventor： Shinan Wang ,  Yutaka Setomoto

IPC: G01N21/00 ,  G01N21/17 ,  B06B1/02 ,  B06B1/06 ,  G01H9/00 ,  H05K1/09 ,  H05K1/11 ,  H05K3/40 ,  G01N29/24 ,  H05K3/00 ,  H05K3/06 ,  H05K3/42

CPC classification number: G01N21/1702 ,  B06B1/0292 ,  B06B1/06 ,  B06B1/0622 ,  G01H9/004 ,  G01N29/24 ,  G01N29/2406 ,  G01N29/2418 ,  G01N29/2437 ,  G01N2021/1706 ,  H01L21/76898 ,  H01L23/49827 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0041 ,  H05K3/06 ,  H05K3/4084 ,  H05K3/42 ,  H05K2201/09854 ,  H05K2203/025

Abstract: In a method of producing a device in which an element structure is provided on a substrate including a through wiring, a through hole is formed so as to extend from a first surface of the substrate to a second surface of the substrate disposed on an opposite side of the substrate to the first surface, the through wiring is formed by filling the through hole with an electrically conductive material, and the element structure is formed on a first surface side. In the step of forming the through hole, a degree of surface irregularities of an inner wall of the through hole is larger on the first surface side than on a second surface side.

公开(公告)号：US20170374747A1

公开(公告)日：2017-12-28

申请号：US15622733

申请日：2017-06-14

Applicant: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.

Inventor： Dror Hurwitz ,  Alex Huang

IPC: H05K3/40 ,  H01L23/00 ,  H05K3/46 ,  H05K1/11 ,  H05K3/26 ,  H05K3/10 ,  H05K3/00 ,  H05K3/34

CPC classification number: H05K3/4007 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2224/81805 ,  H01L2924/00011 ,  H01L2924/01322 ,  H05K1/112 ,  H05K3/0041 ,  H05K3/108 ,  H05K3/26 ,  H05K3/3473 ,  H05K3/4647 ,  H05K2201/09436 ,  H05K2201/10674 ,  H05K2203/025 ,  H05K2203/0278 ,  H05K2203/043 ,  H05K2203/0465 ,  H01L2924/00014

Abstract: A method of attaching a chip to the substrate with an outer layer comprising via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method comprising the steps of: (o) optionally removing organic varnish, (p) positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and (q) applying heat to melt the solder bumps and to wet the ends of the vias with solder.

公开(公告)号：US20170347464A1

公开(公告)日：2017-11-30

申请号：US15536809

申请日：2015-12-21

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD. ,  SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.

Inventor： Kayo HASHIZUME ,  Yoshio OKA ,  Takashi KASUGA ,  Jinjoo PARK ,  Kousuke MIURA ,  Hiroshi UEDA

IPC: H05K3/38 ,  H05K1/09 ,  H05K1/05 ,  H05K1/03 ,  H05K1/02 ,  H05K3/24 ,  B32B15/08

CPC classification number: H05K1/092 ,  B32B15/08 ,  B32B15/088 ,  H05K1/0298 ,  H05K1/03 ,  H05K1/05 ,  H05K1/09 ,  H05K3/1283 ,  H05K3/182 ,  H05K3/24 ,  H05K3/38 ,  H05K3/381 ,  H05K2201/0154 ,  H05K2203/025 ,  H05K2203/095

Abstract: An object is to provide a substrate for a printed wiring board that has good circuit formability while maintaining adhesion strength between a conductive layer (2) and a base film (1). The substrate includes a base film having an insulating property (1) and a conductive layer (2) formed on at least one surface of the base film (1). The maximum height Sz, which is defined in ISO25178, of the surface of the base film (1) is 0.05 μm or more and less than 0.9 μm.

公开(公告)号：US09631279B2

公开(公告)日：2017-04-25

申请号：US14297516

申请日：2014-06-05

Applicant: Kenneth S. Bahl ,  Konstantine Karavakis ,  Steve Carney

Inventor： Kenneth S. Bahl ,  Konstantine Karavakis ,  Steve Carney

IPC: H05K3/10 ,  C23C18/16 ,  C23C18/38 ,  C23C18/20 ,  H05K3/18 ,  H05K3/46

CPC classification number: C23C18/1608 ,  C23C18/204 ,  C23C18/38 ,  H05K3/185 ,  H05K3/4602 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2203/025 ,  H05K2203/0716 ,  H05K2203/107 ,  Y10T29/49165

Abstract: A printed circuit board includes a laminate substrate. The laminate substrate includes catalytic core material that resists metal plating except where a surface of the catalytic material is ablated. Metal traces are formed within in trace channels within the laminate substrate. The channels extend below the surface of the catalytic material.