Integrated circuit reconfiguration techniques
    2.
    发明授权
    Integrated circuit reconfiguration techniques 有权
    集成电路重构技术

    公开(公告)号:US08183883B1

    公开(公告)日:2012-05-22

    申请号:US12762295

    申请日:2010-04-16

    IPC分类号: H03K19/177 G06F7/38

    CPC分类号: H03K19/1776 G06F17/5054

    摘要: A memory configuration circuit is provided. The memory configuration circuit may be integrated into a programmable logic device (PLD) and as such, may be used to configure and reconfigure specific elements in the PLD. The memory configuration circuit includes a comparator circuit and a counter. The comparator circuit is coupled to receive two data words from two different memory configuration sources. The comparator circuit compares the two data words received before writing one of the data words to a configuration memory. One of the data words may be written to the configuration memory if the two data words compared are not equal. The counter increments the address of the memory configuration sources so that a next data word can be processed after the current data word is processed.

    摘要翻译: 提供存储器配置电路。 存储器配置电路可以集成到可编程逻辑器件(PLD)中,并且因此可用于配置和重新配置PLD中的特定元件。 存储器配置电路包括比较器电路和计数器。 比较器电路被耦合以从两个不同的存储器配置源接收两个数据字。 比较器电路将在将一个数据字写入之前接收的两个数据字与配置存储器进行比较。 如果所比较的两个数据字不相等,则可以将一个数据字写入配置存储器。 计数器增加存储器配置源的地址,以便在处理当前数据字之后处理下一个数据字。

    Gain matrix for hierarchical circuit partitioning
    3.
    发明授权
    Gain matrix for hierarchical circuit partitioning 失效
    增益矩阵用于分层电路划分

    公开(公告)号:US06212668B1

    公开(公告)日:2001-04-03

    申请号:US08863880

    申请日:1997-05-27

    IPC分类号: G06F1750

    CPC分类号: G06F17/5072

    摘要: A method for partitioning a group of cells in a network into a set of disjoint blocks of cells. The network is represented by a hierarchical graph with each level representing a hierarchy of resources, leaf nodes representing the blocks of cells, and edges representing interconnections between resources. A gain matrix is formed by combining a gain vector for each level of hierarchy for each possible move. Cells are moved between leaf nodes based on the gain matrix computed.

    摘要翻译: 一种用于将网络中的一组小区划分成一组不相交的小区块的方法。 网络由分层图表示,每个级别表示资源层级,表示单元块的叶节点和表示资源之间互连的边。 通过为每个可能的移动组合用于每层级的增益矢量来形成增益矩阵。 基于计算的增益矩阵,在叶节点之间移动细胞。

    Methods for partitioning circuits in order to allocate elements among
multiple circuit groups
    4.
    发明授权
    Methods for partitioning circuits in order to allocate elements among multiple circuit groups 失效
    划分电路以便在多个电路组中分配元件的方法

    公开(公告)号:US5659717A

    公开(公告)日:1997-08-19

    申请号:US508401

    申请日:1995-07-31

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5072

    摘要: Improved circuit partitioning methods are provided which combine the advantage of multiple starting positions of the random initial placement approach with the advantage of optimal starting positions of the greedy initial placement approach, by starting with greedy initial placement and modifying partitioning constraints on subsequent passes so that each pass begins in a new position, In addition, the partitioning goals of interconnection minimization and resource utilization efficiency may be prioritized according to a design goal by manipulating the manner in which partitioning constraints are changed during each partitioning pass. Furthermore a user may adjust the weight of the benefits for eliminating existing interconnections and the weight of the penalties for adding new interconnections in accordance with a design goal.

    摘要翻译: 提供了改进的电路划分方法,其结合了随机初始放置方法的多个起始位置的优点和贪婪初始放置方法的最佳起始位置的优点,从贪婪初始放置开始,并修改后续通过的分区约束, 通过从一个新的位置开始。另外,可以根据设计目标优化互连最小化和资源利用效率的分区目标,通过操纵在每次分区过程中分区约束被改变的方式。 此外,用户可以调整用于消除现有互连的益处的重量以及根据设计目标添加新互连的惩罚的重量。

    Method and apparatus for circuit block reconfiguration EDA
    5.
    发明授权
    Method and apparatus for circuit block reconfiguration EDA 有权
    电路块重构EDA的方法和装置

    公开(公告)号:US08595670B1

    公开(公告)日:2013-11-26

    申请号:US12719298

    申请日:2010-03-08

    IPC分类号: G06F17/50

    摘要: Methods and apparatus are described for efficiently performing EDA processing to arrive at a hardware definition for a varying fraction of a large circuit design. EDA processing is conducted targeting a pseudo hardware device with sufficient capacity to embody circuitry for the varying fraction, but substantially less than the true hardware target. The novel methods and apparatus may be beneficially employed to produce reconfiguration information for circuits that include programmable logic, for example.

    摘要翻译: 描述了用于有效执行EDA处理以达到大电路设计的不同部分的硬件定义的方法和装置。 对具有足够容量的伪硬件设备进行EDA处理,以实现不同部分的电路,但是实质上小于真正的硬件目标。 可以有益地使用新颖的方法和装置来产生例如包括可编程逻辑的电路的重新配置信息。

    Hierarchical circuit partitioning using sliding windows
    6.
    发明授权
    Hierarchical circuit partitioning using sliding windows 失效
    使用滑动窗口的分层电路划分

    公开(公告)号:US06301694B1

    公开(公告)日:2001-10-09

    申请号:US08936112

    申请日:1997-09-24

    IPC分类号: G06F1750

    CPC分类号: G06F17/5072

    摘要: Systems and methods of hierarchical circuit partitioning are provided. More specifically, the invention utilizes a sliding window which is moved over portions of a hierarchical structure representing a programmable logic device. The window includes some but not all containers of the hierarchical structure so that logic cells may be partitioned within the window. After the logic cells are partitioned in the window, the window is moved to a different location of the hierarchical structure. By utilizing a sliding window, the invention is able to recursively partition logic cells into portions of the hierarchical structure which increases the overall efficiency of the partitioning.

    摘要翻译: 提供了分层电路划分的系统和方法。 更具体地说,本发明利用了滑动窗口,该滑动窗口在表示可编程逻辑设备的层次结构的部分上移动。 该窗口包括一些但不是所有层次结构的容器,使得逻辑单元可以在窗口内被分割。 在窗口中分割逻辑单元之后,将窗口移动到分层结构的不同位置。 通过利用滑动窗口,本发明能够将逻辑单元递归地分成分层结构的部分,这增加了分区的整体效率。

    Fitting for incremental compilation of electronic designs
    7.
    发明授权
    Fitting for incremental compilation of electronic designs 失效
    适用于电子设计的增量编译

    公开(公告)号:US6102964A

    公开(公告)日:2000-08-15

    申请号:US958436

    申请日:1997-10-27

    摘要: A technique is disclosed for efficiently placing logic cells from an electronic design during an incremental recompile. This is accomplished by fixing in place as many logic cells as possible during the recompile procedure. To understand how this works, recognize than an "original electronic design" has already been fully compiled. Now, a user has made one or more changes to the original electronic design to produce a "changed electronic design." The disclosed technique fits the changed electronic design, during incremental recompile, without effecting too much of the logic previously fit during compilation of the original electronic design. Initially, a compiler attempts to fit logic cells of the changed portion of the electronic design onto available logic elements of the hardware device while confining logic cells from the unchanged portion of the changed electronic design to their original positions.If this fails, the compiler allows logic cells from the unchanged portion of the changed electronic design to shift by a limited amount to other logic elements within the target hardware device. At first, this shifting is fairly constrained in order to preserve as much of the original compilation's placement as possible. However, if fitting can not be accomplished under these constraints, gradually the constraints are lifted, until a fit is achieved.

    摘要翻译: 公开了一种用于在增量重新编译期间从电子设计有效地放置逻辑单元的技术。 这是通过在重新编译过程中尽可能多地固定逻辑单元来实现的。 要了解如何运作,认识不到“原创电子设计”已经完全编译。 现在,用户对原始电子设计进行了一个或多个更改以产生“改变的电子设计”。 所公开的技术适合改变的电子设计,在增量重新编译期间,而不会在原始电子设计的编译期间太多的先前适合的逻辑。 最初,编译器尝试将电子设计的改变的部分的逻辑单元适配到硬件设备的可用逻辑元件,同时将来自改变的电子设计的未改变部分的逻辑单元限制到其原始位置。 如果失败,编译器允许来自改变的电子设计的未改变部分的逻辑单元向目标硬件设备内的其他逻辑元件移动有限的量。 起初,这种转变是相当有限的,以便尽可能多地保留原始的编译位置。 然而,如果在这些约束条件下不能完成拟合,则逐渐地解除约束,直到实现拟合。

    Programmable logic array integrated circuit devices with flexible carry
chains
    8.
    发明授权
    Programmable logic array integrated circuit devices with flexible carry chains 失效
    具有灵活携带链的可编程逻辑阵列集成电路器件

    公开(公告)号:US5631576A

    公开(公告)日:1997-05-20

    申请号:US522554

    申请日:1995-09-01

    申请人: Fung F. Lee John Tse

    发明人: Fung F. Lee John Tse

    IPC分类号: H03K19/177

    CPC分类号: H03K19/17728 H03K19/17704

    摘要: A programmable logic array integrated circuit has a plurality of logic modules, each of which is programmable to perform any of several logic functions. One such function is the performance of one place of binary addition yielding a sum out signal and a carry out signal. In addition to a dedicated carry chain which conveys the carry out signal of each logic module to the carry in input of another predetermined logic module, circuitry is provided for allowing the carry out signal of each logic module to be alternatively routed through the more general interconnection circuitry of the device. This increases the flexibility of routing of the carry out signals, thereby increasing the flexibility of use of the integrated circuit. Improved circuitry for handling a carry in signal may also be provided in each logic module.

    摘要翻译: 可编程逻辑阵列集成电路具有多个逻辑模块,每个逻辑模块可编程以执行若干逻辑功能中的任何一个。 一个这样的功能是执行二进制加法的一个地方,产生一个和出信号和一个进位信号。 除了将每个逻辑模块的进位信号传送到另一预定逻辑模块的输入中的进位之外的专用进位链之外,提供电路以允许每个逻辑模块的进位信号通过更一般的互连 设备的电路。 这增加了进位信号的路由的灵活性,从而增加了集成电路的使用的灵活性。 也可以在每个逻辑模块中提供用于处理信号进位的改进的电路。