公开(公告)号：US09417883B2

公开(公告)日：2016-08-16

申请号：US13608221

申请日：2012-09-10

Applicant: Alexander G. MacInnis ,  Jose′ R. I. Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

Inventor： Alexander G. MacInnis ,  Jose′ R. I. Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

IPC: H04N19/423 ,  G06F9/38 ,  H04N19/176 ,  H04N19/70 ,  H04N19/122 ,  H04N19/129 ,  H04N19/61 ,  H04N19/60 ,  H04N19/12 ,  H04N19/91 ,  H04N19/157 ,  H04N19/44 ,  H04N19/82 ,  H04N19/90 ,  H04N19/625

CPC classification number: G06F9/3861 ,  G06F9/3877 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/625 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90 ,  H04N19/91

Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.