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公开(公告)号：US09417883B2
公开(公告)日：2016-08-16
申请号：US13608221
申请日：2012-09-10
IPC分类号： H04N19/423 , G06F9/38 , H04N19/176 , H04N19/70 , H04N19/122 , H04N19/129 , H04N19/61 , H04N19/60 , H04N19/12 , H04N19/91 , H04N19/157 , H04N19/44 , H04N19/82 , H04N19/90 , H04N19/625
CPC分类号： G06F9/3861 , G06F9/3877 , H04N19/12 , H04N19/122 , H04N19/129 , H04N19/157 , H04N19/176 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/82 , H04N19/90 , H04N19/91
摘要： System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.
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公开(公告)号：US08005147B2
公开(公告)日：2011-08-23
申请号：US11400949
申请日：2006-04-05
IPC分类号： H04N7/18
CPC分类号： G06F9/3861 , G06F9/3877 , H04N19/12 , H04N19/122 , H04N19/129 , H04N19/13 , H04N19/157 , H04N19/176 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/70 , H04N19/82 , H04N19/90
摘要： A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel. The variable-length decoders operate as part of a pipeline wherein the variable-length decoders alternate, stage-by-stage, decoding macroblocks.
摘要翻译： 一种用于解码数字视频数据流的系统和方法。 在一个方面，多个硬件加速模块与核心处理器一起使用。 加速器在解码管线中操作，其中在任何给定阶段，每个加速器对视频数据的特定宏块进行操作。 在随后的流水线阶段，每个加速器对数据流中的下一个宏块进行工作，该前一阶段的另一个加速器工作。 核心处理器在每个阶段轮询所有加速器。 当所有加速器在给定阶段完成任务时，核心处理器启动下一阶段。 在另一方面，采用两个可变长度解码器来同时解码视频帧的两个宏块行。 每个可变长度解码器用于对分配的行进行解码，并行并行地进行可变长度解码。 可变长度解码器作为流水线的一部分进行操作，其中可变长度解码器逐级交替解码宏块。
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公开(公告)号：US07096245B2
公开(公告)日：2006-08-22
申请号：US10114619
申请日：2002-04-01
申请人： Vivian Hsiun , Alexander G. MacInnis , Xiaodong Xie , Sheng Zhong
发明人： Vivian Hsiun , Alexander G. MacInnis , Xiaodong Xie , Sheng Zhong
IPC分类号： G06F17/14
CPC分类号： H04N19/90 , H04N19/12 , H04N19/122 , H04N19/129 , H04N19/157 , H04N19/176 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/70 , H04N19/82 , H04N19/91
摘要： The present invention provides an apparatus and method for providing a programmable inverse discrete cosine transform, wherein the transform coefficients are loaded into a memory area of a core transform device and a variety of coding standards can thereby be handled by the same programmable core device. The core device is configured to process a certain sized data block, and the incoming source blocks are converted to conform to this size. After transformation, the proper sized result can be extracted from the transform device output. A switchable speed-up mode provides for 4-point transforms, rather than 8-point transforms. Alternatively, the invention also provides for dedicated transform hardware to be switchably used in conjunction with programmable transform hardware, depending upon the type of coding being used, and the speed of inverse transform desired.
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公开(公告)号：US07007031B2
公开(公告)日：2006-02-28
申请号：US10114886
申请日：2002-04-01
CPC分类号： G06F9/3861 , G06F9/3877 , H04N19/12 , H04N19/122 , H04N19/129 , H04N19/157 , H04N19/176 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/70 , H04N19/82 , H04N19/90 , Y10S707/99942
摘要： System and method of data unit management in a decoding system employing a decoding pipeline. Each incoming data unit is assigned a memory element and is stored in the assigned memory element. Each decoding module gets the data to be operated on, as well as the control data, for a given data unit from the assigned memory element. Each decoding module, after performing its decoding operations on the data unit, deposits the newly processed data back into the same memory element. In one embodiment, the assigned memory locations comprise a header portion for holding the control data corresponding to the data unit and a data portion for holding the substantive data of the data unit. The header information is written to the header portion of the assigned memory element once and accessed by the various decoding modules throughout the decoding pipeline as needed. The data portion of memory is used/shared by multiple decoding modules.
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公开(公告)号：US07881385B2
公开(公告)日：2011-02-01
申请号：US11015555
申请日：2004-12-17
IPC分类号： H04N7/18
CPC分类号： G06F9/3861 , G06F9/3877 , H04N19/12 , H04N19/122 , H04N19/129 , H04N19/157 , H04N19/176 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/82 , H04N19/90 , H04N19/91
摘要： System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.
摘要翻译： 用于解码数字视频数据的系统和方法。 解码系统采用辅助核心处理器执行所选解码任务的硬件加速器。 硬件加速器可配置为支持多种现有和将来的编码/解码格式。 加速器可配置为支持落入基于DCT的熵解码的块运动补偿压缩算法的一般类别中的任何现有或将来的编码/解码格式。 硬件加速器示例性地包括可编程熵解码器，逆量化模块，反相离散余弦变换模块，像素滤波器，运动补偿模块和去块滤波器。 硬件加速器在解码流水线中起作用，其中在流水线中的任何给定阶段，在给定宏块上执行给定功能的同时，数据流中的下一个宏块正在通过管道中的先前功能进行处理。
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公开(公告)号：US20120328000A1
公开(公告)日：2012-12-27
申请号：US13608192
申请日：2012-09-10
IPC分类号： H04N7/26
CPC分类号： G06F9/3861 , G06F9/3877 , H04N19/12 , H04N19/122 , H04N19/129 , H04N19/157 , H04N19/176 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/82 , H04N19/90 , H04N19/91
摘要： System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.
摘要翻译： 用于解码数字视频数据的系统和方法。 解码系统采用辅助核心处理器执行所选解码任务的硬件加速器。 硬件加速器可配置为支持多种现有和将来的编码/解码格式。 加速器可配置为支持落入基于DCT的熵解码的块运动补偿压缩算法的一般类别中的任何现有或将来的编码/解码格式。 硬件加速器示例性地包括可编程熵解码器，逆量化模块，反相离散余弦变换模块，像素滤波器，运动补偿模块和去块滤波器。 硬件加速器在解码流水线中起作用，其中在流水线中的任何给定阶段，在给定宏块上执行给定功能的同时，数据流中的下一个宏块正在通过管道中的先前功能进行处理。
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公开(公告)号：US08229002B2
公开(公告)日：2012-07-24
申请号：US13018840
申请日：2011-02-01
IPC分类号： H04N7/18
CPC分类号： G06F9/3861 , G06F9/3877 , H04N19/12 , H04N19/122 , H04N19/129 , H04N19/157 , H04N19/176 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/82 , H04N19/90 , H04N19/91
摘要： System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.
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公开(公告)号：US09329871B2
公开(公告)日：2016-05-03
申请号：US13608192
申请日：2012-09-10
IPC分类号： H04N7/18 , G06F9/38 , H04N19/176 , H04N19/70 , H04N19/122 , H04N19/129 , H04N19/61 , H04N19/60 , H04N19/12 , H04N19/91 , H04N19/157 , H04N19/44 , H04N19/82 , H04N19/423 , H04N19/90 , H04N19/625
CPC分类号： G06F9/3861 , G06F9/3877 , H04N19/12 , H04N19/122 , H04N19/129 , H04N19/157 , H04N19/176 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/82 , H04N19/90 , H04N19/91
摘要： System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.
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公开(公告)号：US20130022105A1
公开(公告)日：2013-01-24
申请号：US13608221
申请日：2012-09-10
IPC分类号： H04N7/12
CPC分类号： G06F9/3861 , G06F9/3877 , H04N19/12 , H04N19/122 , H04N19/129 , H04N19/157 , H04N19/176 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/82 , H04N19/90 , H04N19/91
摘要： System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.
摘要翻译： 用于解码数字视频数据的系统和方法。 解码系统采用辅助核心处理器执行所选解码任务的硬件加速器。 硬件加速器可配置为支持多种现有和将来的编码/解码格式。 加速器可配置为支持落入基于DCT的熵解码的块运动补偿压缩算法的一般类别中的任何现有或将来的编码/解码格式。 硬件加速器示例性地包括可编程熵解码器，逆量化模块，反相离散余弦变换模块，像素滤波器，运动补偿模块和去块滤波器。 硬件加速器在解码流水线中起作用，其中在流水线中的任何给定阶段，在给定宏块上执行给定功能的同时，数据流中的下一个宏块正在通过管道中的先前功能进行处理。
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公开(公告)号：US08284844B2
公开(公告)日：2012-10-09
申请号：US10114798
申请日：2002-04-01
IPC分类号： H04N7/18
CPC分类号： G06F9/3861 , G06F9/3877 , H04N19/12 , H04N19/122 , H04N19/129 , H04N19/157 , H04N19/176 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/82 , H04N19/90 , H04N19/91
摘要： System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.
摘要翻译： 用于解码数字视频数据的系统和方法。 解码系统采用辅助核心处理器执行所选解码任务的硬件加速器。 硬件加速器可配置为支持多种现有和将来的编码/解码格式。 加速器可配置为支持落入基于DCT的熵解码的块运动补偿压缩算法的一般类别中的任何现有或将来的编码/解码格式。 硬件加速器示例性地包括可编程熵解码器，逆量化模块，反相离散余弦变换模块，像素滤波器，运动补偿模块和去块滤波器。 硬件加速器在解码流水线中起作用，其中在流水线中的任何给定阶段，在给定宏块上执行给定功能的同时，数据流中的下一个宏块正在通过管道中的先前功能进行处理。
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