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1.发明申请NEGATIVE CAPACITANCE LOGIC DEVICE, CLOCK GENERATOR INCLUDING THE SAME AND METHOD OF OPERATING CLOCK GENERATOR 有权负电容逻辑器件，包括其的时钟发生器和操作时钟发生器的方法公开(公告)号：US20160211849A1
公开(公告)日：2016-07-21
申请号：US14614884
申请日：2015-02-05
申请人： Min Cheol Shin , Jae Hyun Lee , Doo Hyung Kang , Jun Beom Seo , Woo Jin Jeong
发明人： Min Cheol Shin , Jae Hyun Lee , Doo Hyung Kang , Jun Beom Seo , Woo Jin Jeong
IPC分类号： H03K19/16 , H03L7/26 , H03B15/00 , H03K19/0185
CPC分类号： H03K19/16 , B82Y25/00 , G11C11/16 , H01L29/66984 , H01L43/02 , H01L43/08 , H01L43/10 , H03B15/006 , H03K19/018578
摘要： A negative capacitance logic device includes a first field effect transistor (FET) and a second FET. The first FET is coupled between a power supply voltage and an output node, and the first FET includes a ferroelectric having a negative capacitance. The second FET is coupled between the output node and a ground voltage, and the second FET includes a ferroelectric having a negative capacitance. The negative capacitance logic differentiates an input voltage applied to an input node to provide an output voltage at the output node.
摘要翻译： 负电容逻辑器件包括第一场效应晶体管（FET）和第二FET。 第一FET耦合在电源电压和输出节点之间，并且第一FET包括具有负电容的铁电体。 第二FET耦合在输出节点和接地电压之间，第二FET包括具有负电容的铁电体。 负电容逻辑区分施加到输入节点的输入电压以在输出节点处提供输出电压。
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2.发明授权Negative capacitance logic device, clock generator including the same and method of operating clock generator 有权负电容逻辑器件，时钟发生器包括相同的操作时钟发生器和方法公开(公告)号：US09484924B2
公开(公告)日：2016-11-01
申请号：US14614884
申请日：2015-02-05
申请人： Min Cheol Shin , Jae Hyun Lee , Doo Hyung Kang , Jun Beom Seo , Woo Jin Jeong
发明人： Min Cheol Shin , Jae Hyun Lee , Doo Hyung Kang , Jun Beom Seo , Woo Jin Jeong
IPC分类号： H03K3/315 , H03L7/26 , H03K19/16 , H03K19/0185 , H03B15/00 , H01L29/66 , B82Y25/00 , H01L43/02 , G11C11/16 , H01L43/10
CPC分类号： H03K19/16 , B82Y25/00 , G11C11/16 , H01L29/66984 , H01L43/02 , H01L43/08 , H01L43/10 , H03B15/006 , H03K19/018578
摘要： A negative capacitance logic device includes a first field effect transistor (FET) and a second FET. The first FET is coupled between a power supply voltage and an output node, and the first FET includes a ferroelectric having a negative capacitance. The second FET is coupled between the output node and a ground voltage, and the second FET includes a ferroelectric having a negative capacitance. The negative capacitance logic differentiates an input voltage applied to an input node to provide an output voltage at the output node.
摘要翻译： 负电容逻辑器件包括第一场效应晶体管（FET）和第二FET。 第一FET耦合在电源电压和输出节点之间，并且第一FET包括具有负电容的铁电体。 第二FET耦合在输出节点和接地电压之间，第二FET包括具有负电容的铁电体。 负电容逻辑区分施加到输入节点的输入电压以在输出节点处提供输出电压。
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