公开(公告)号：US20130146962A1

公开(公告)日：2013-06-13

申请号：US13598942

申请日：2012-08-30

申请人： Jung Ryul AHN ,  Yun Kyoung Lee

发明人： Jung Ryul AHN ,  Yun Kyoung Lee

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11565 ,  H01L27/11568

摘要： A semiconductor device includes a plurality of first trenches having a first depth formed in a semiconductor substrate, a plurality of second trenches having a second depth formed in the semiconductor substrate, wherein the second depth is different from the first depth and the second trenches are formed between the first trenches, a plurality of isolation layers formed at the plurality of first trenches and the plurality of second trenches, wherein the isolation layers have upper portions formed above the semiconductor substrate, and a plurality of memory cells formed over the semiconductor substrate between the isolation layers.

摘要翻译： 半导体器件包括多个第一沟槽，其具有形成在半导体衬底中的第一深度，多个第二沟槽，其具有形成在半导体衬底中的第二深度，其中第二深度不同于第一深度，并且形成第二沟槽 在所述第一沟槽之间，形成在所述多个第一沟槽和所述多个第二沟槽中的多个隔离层，其中所述隔离层具有形成在所述半导体衬底上方的上部，以及形成在所述半导体衬底之上的多个存储单元 隔离层。

公开(公告)号：US08111557B2

公开(公告)日：2012-02-07

申请号：US12647586

申请日：2009-12-28

申请人： Jung Ryul Ahn

发明人： Jung Ryul Ahn

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A nonvolatile memory device and a method of programming the device includes storing first data in first main and sub-registers and storing second data in second main and sub-registers, performing first program and verification operations on first memory cells based on the first data stored in the first main register, storing a result of the first verification operation in the first main register, performing a second program operation on second memory cells based on the second data stored in the second main register, changing the result of the first verification operation, stored in the first main register, into the first data stored in the first sub-register, performing an additional verification operation on the first memory cells on which the first verification operation has been completed, storing a result of the additional verification operation in the first main register, and performing a second verification operation on the second memory cells.

摘要翻译： 非易失性存储器件和编程器件的方法包括：将第一数据存储在第一主存储器和子寄存器中，并将第二数据存储在第二主寄存器和子寄存器中，基于存储的第一数据对第一存储器单元执行第一程序和验证操作 在第一主寄存器中，将第一验证操作的结果存储在第一主寄存器中，基于存储在第二主寄存器中的第二数据对第二存储器单元执行第二编程操作，改变第一验证操作的结果， 存储在第一主寄存器中的第一存储单元中的第一数据存储在第一子寄存器中，对已经完成了第一验证操作的第一存储单元执行附加验证操作，将附加验证操作的结果存储在第一主寄存器中 主寄存器，并对第二存储单元执行第二验证操作。

公开(公告)号：US20110124195A1

公开(公告)日：2011-05-26

申请号：US13055322

申请日：2009-07-22

申请人： Hyu-Bum Park ,  Dae-Sung Kim ,  Jong-Kwan Park ,  Jung-Ryul Ahn

发明人： Hyu-Bum Park ,  Dae-Sung Kim ,  Jong-Kwan Park ,  Jung-Ryul Ahn

IPC分类号： H01L21/306 ,  C09K13/00 ,  C09K13/02 ,  C09K13/06

CPC分类号： C09K3/1463 ,  C09G1/02 ,  H01L21/31053

摘要： Provided are a chemical mechanical polishing (CMP) composition used for polishing a semiconductor device which contains polysilicon film and insulator, and a chemical mechanical polishing method thereof. The CMP composition is especially useful in a isolation CMP process for semiconductor devices. Provided is a highly selective CMP composition containing a polysilicon polish finisher which can selectively polish semiconductor insulators since it uses a polysilicon film as a polish finishing film.

摘要翻译： 提供了用于研磨含有多晶硅膜和绝缘体的半导体器件的化学机械抛光（CMP）组合物及其化学机械抛光方法。 CMP组合物在用于半导体器件的隔离CMP工艺中是特别有用的。 提供了一种高选择性CMP组合物，其包含多晶硅抛光整理剂，其可以选择性地抛光半导体绝缘体，因为它使用多晶硅膜作为抛光整理膜。

公开(公告)号：US20100246273A1

公开(公告)日：2010-09-30

申请号：US12647586

申请日：2009-12-28

申请人： Jung Ryul Ahn

发明人： Jung Ryul Ahn

IPC分类号： G11C16/06 ,  G11C7/10

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A nonvolatile memory device and a method of programming the device includes storing first data in first main and sub-registers and storing second data in second main and sub-registers, performing first program and verification operations on first memory cells based on the first data stored in the first main register, storing a result of the first verification operation in the first main register, performing a second program operation on second memory cells based on the second data stored in the second main register, changing the result of the first verification operation, stored in the first main register, into the first data stored in the first sub-register, performing an additional verification operation on the first memory cells on which the first verification operation has been completed, storing a result of the additional verification operation in the first main register, and performing a second verification operation on the second memory cells.

摘要翻译： 非易失性存储器件和编程器件的方法包括：将第一数据存储在第一主存储器和子寄存器中，并将第二数据存储在第二主寄存器和子寄存器中，基于存储的第一数据对第一存储器单元执行第一程序和验证操作 在第一主寄存器中，将第一验证操作的结果存储在第一主寄存器中，基于存储在第二主寄存器中的第二数据对第二存储器单元执行第二编程操作，改变第一验证操作的结果， 存储在第一主寄存器中的第一存储单元中的第一数据存储在第一子寄存器中，对已经完成了第一验证操作的第一存储单元执行附加验证操作，将附加验证操作的结果存储在第一主寄存器中 主寄存器，并对第二存储单元执行第二验证操作。

公开(公告)号：US07662697B2

公开(公告)日：2010-02-16

申请号：US11416738

申请日：2006-05-02

申请人： Jung Ryul Ahn ,  Byung Soo Park

发明人： Jung Ryul Ahn ,  Byung Soo Park

IPC分类号： H01L21/76

CPC分类号： H01L21/76232

摘要： A method of forming a semiconductor device includes etching a semiconductor substrate to form a first trench having a first width and a first depth; etching the semiconductor substrate to form a second trench having a second width and a second depth, the second trench overlapping the first trench, the second width being greater than the first width, the second depth being less than the first depth, whereby a trench having a dual structure is formed; and forming a first isolation structure within the trench having the dual structure. An embodiment of the present invention relates to a method of forming an isolation structure of a semiconductor device.

摘要翻译： 形成半导体器件的方法包括蚀刻半导体衬底以形成具有第一宽度和第一深度的第一沟槽; 蚀刻所述半导体衬底以形成具有第二宽度和第二深度的第二沟槽，所述第二沟槽与所述第一沟槽重叠，所述第二宽度大于所述第一宽度，所述第二深度小于所述第一深度，由此具有 形成双重结构; 以及在具有双重结构的沟槽内形成第一隔离结构。 本发明的实施例涉及一种形成半导体器件的隔离结构的方法。

公开(公告)号：US20090053871A1

公开(公告)日：2009-02-26

申请号：US12124024

申请日：2008-05-20

申请人： Jung Ryul AHN

发明人： Jung Ryul AHN

IPC分类号： H01L21/336

CPC分类号： H01L27/105 ,  H01L27/11573

摘要： A semiconductor memory device and method of fabricating a semiconductor memory device, wherein a tunnel insulating layer, a first charge trap layer and an isolation mask layer are sequentially stacked over a semiconductor substrate in which a cell region and a peri region are defined. The isolation mask layer, the first charge trap layer, the tunnel insulating layer and the semiconductor substrate are etched to thereby form trenches. An isolation layer is formed within each trench. The first charge trap layer is exposed by removing the isolation mask layer formed in the cell region. A second charge trap layer is formed on the exposed first charge trap layer and the isolation layer. A blocking layer and a control gate are formed over the semiconductor substrate in which the second charge trap layer is formed.

摘要翻译： 一种半导体存储器件和半导体存储器件的制造方法，其中隧道绝缘层，第一电荷陷阱层和隔离掩模层依次层叠在其中限定了单元区域和周边区域的半导体衬底上。 蚀刻隔离掩模层，第一电荷阱层，隧道绝缘层和半导体衬底，从而形成沟槽。 在每个沟槽内形成隔离层。 通过去除形成在单元区域中的隔离掩模层来暴露第一电荷陷阱层。 在暴露的第一电荷陷阱层和隔离层上形成第二电荷陷阱层。 在其上形成有第二电荷陷阱层的半导体衬底上形成阻挡层和控制栅极。

公开(公告)号：US06759299B2

公开(公告)日：2004-07-06

申请号：US10321720

申请日：2002-12-18

申请人： Young Bok Lee ,  Sung Mun Jung ,  Jung Ryul Ahn

发明人： Young Bok Lee ,  Sung Mun Jung ,  Jung Ryul Ahn

IPC分类号： H01L218247

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： The present invention relates to a method of manufacturing a flash memory device. In the method, a low-voltage transistor is formed to have a DDD structure same to a high-voltage transistor when a peripheral region is formed in the manufacture process of the flash memory device. As the process for forming the LDD structure for the low voltage is omitted, the cost is reduced in the entire process of manufacturing the flash memory device. Also, as the junction breakdown voltage of the low-voltage transistor is increased and current is increased, the device characteristics is improved

摘要翻译： 本发明涉及一种制造闪速存储器件的方法。 在该方法中，当在闪速存储器件的制造过程中形成周边区域时，形成低压晶体管，以使DDD结构与高电压晶体管相同。 由于省略了用于形成用于低电压的LDD结构的工艺，所以在制造闪存器件的整个过程中降低了成本。 此外，随着低压晶体管的结击穿电压增加并且电流增加，器件特性得到改善

公开(公告)号：US08759902B2

公开(公告)日：2014-06-24

申请号：US13333893

申请日：2011-12-21

申请人： Jung-Ryul Ahn

发明人： Jung-Ryul Ahn

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/66 ,  H01L21/28

CPC分类号： H01L27/11578 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A non-volatile memory device includes a plurality of gate electrodes stacked over a semiconductor substrate and stretched in a first direction along the semiconductor substrate and a plurality of junction layers having a first region protruding from the semiconductor substrate and crossing the gate electrodes and a second region formed between the gate electrodes.

摘要翻译： 非易失性存储器件包括堆叠在半导体衬底上并沿着半导体衬底沿第一方向拉伸的多个栅极电极以及具有从半导体衬底突出并与栅电极交叉的第一区域的多个接合层， 形成在栅电极之间的区域。

公开(公告)号：US20130146984A1

公开(公告)日：2013-06-13

申请号：US13601437

申请日：2012-08-31

申请人： Jung Ryul AHN

发明人： Jung Ryul AHN

IPC分类号： H01L21/762 ,  H01L29/78

CPC分类号： H01L27/11519 ,  H01L27/11524 ,  H01L29/40114

摘要： A semiconductor device includes isolation layers formed at isolation regions of a semiconductor substrate, silicon patterns formed over the semiconductor substrate between the isolation layers, insulating layers formed between the silicon patterns and the semiconductor substrate, and junctions formed in the semiconductor substrate between the silicon patterns, wherein each of the silicon patterns has a sloped top surface.

摘要翻译： 半导体器件包括形成在半导体衬底的隔离区域处的隔离层，形成在隔离层之间的半导体衬底上的硅图案，形成在硅图案和半导体衬底之间的绝缘层，以及在硅图案之间形成在半导体衬底中的结 ，其中每个硅图案具有倾斜的顶表面。

公开(公告)号：US08351270B2

公开(公告)日：2013-01-08

申请号：US13344349

申请日：2012-01-05

申请人： Jung Ryul Ahn

发明人： Jung Ryul Ahn

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A nonvolatile memory device and a method of programming the device includes storing first data in first main and sub-registers and storing second data in second main and sub-registers, performing first program and verification operations on first memory cells based on the first data stored in the first main register, storing a result of the first verification operation in the first main register, performing a second program operation on second memory cells based on the second data stored in the second main register, changing the result of the first verification operation, stored in the first main register, into the first data stored in the first sub-register, performing an additional verification operation on the first memory cells on which the first verification operation has been completed, storing a result of the additional verification operation in the first main register, and performing a second verification operation on the second memory cells.

摘要翻译： 非易失性存储器件和编程器件的方法包括：将第一数据存储在第一主存储器和子寄存器中，并将第二数据存储在第二主寄存器和子寄存器中，基于存储的第一数据对第一存储器单元执行第一程序和验证操作 在第一主寄存器中，将第一验证操作的结果存储在第一主寄存器中，基于存储在第二主寄存器中的第二数据对第二存储器单元执行第二编程操作，改变第一验证操作的结果， 存储在第一主寄存器中的第一存储单元中的第一数据存储在第一子寄存器中，对已经完成了第一验证操作的第一存储单元执行附加验证操作，将附加验证操作的结果存储在第一主寄存器中 主寄存器，并对第二存储单元执行第二验证操作。