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    Semiconductor memory device comprising memory cells with floating gate electrode and method of production
    1.
    发明授权
    Semiconductor memory device comprising memory cells with floating gate electrode and method of production 有权
    半导体存储器件包括具有浮栅电极的存储单元和制造方法

    公开(公告)号：US07250651B2

    公开(公告)日：2007-07-31

    申请号：US10921766

    申请日：2004-08-19

    申请人： Karl-Heinz Küsters ,  Josef Willer ,  Corvin Liaw

    发明人： Karl-Heinz Küsters ,  Josef Willer ,  Corvin Liaw

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L31/062

    CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/51 ,  H01L29/66825 ,  H01L29/792

    摘要： Transistor bodies of semiconductor material located at a main surface of a semiconductor substrate between shallow trench isolations are provided with a rounded or curved upper surface. A floating gate electrode is arranged above said upper surface and electrically insulated from the semiconductor material by a tunnel dielectric having essentially the same tiny thickness throughout a primary tunnel area encompassing the area of curvature. The floating gate electrode may bridge the transistor body and is covered with a coupling dielectric provided for a control gate electrode, which forms part of a wordline.

    摘要翻译： 位于浅沟槽隔离物之间的半导体衬底的主表面处的半导体材料的晶体管本体具有圆形或弯曲的上表面。 浮栅电极布置在所述上​​表面之上并且通过隧道电介质与半导体材料电绝缘，所述隧道电介质具有贯穿所述曲率区域的主隧道区域具有基本上相同的微小厚度。 浮栅电极可以桥接晶体管本体，并被形成为形成字线一部分的控制栅电极的耦合电介质覆盖。

    One-transistor memory cell configuration and method for its fabrication
    2.
    发明授权
    One-transistor memory cell configuration and method for its fabrication 失效
    单晶体管存储单元配置及其制造方法

    公开(公告)号：US06590249B2

    公开(公告)日：2003-07-08

    申请号：US10166813

    申请日：2002-06-11

    申请人： Karl Heinz Küsters ,  Dietmar Temmler

    发明人： Karl Heinz Küsters ,  Dietmar Temmler

    IPC分类号： H01L27108

    CPC分类号： H01L27/10867 ,  H01L27/10832 ,  H01L27/1203

    摘要： In a method for fabricating a dynamic memory cell in a semiconductor substrate having a trench capacitor 1 and a selection transistor 2 and a semiconductor memory having such a memory cell, a dielectric insulator layer 17, 201 is formed between the selection transistor and the trench capacitor, a first electrode region 203 of the selection transistor essentially being arranged above a block-type inner electrode 102 of the trench capacitor and being connected to said electrode via a contact opening 213 in the dielectric insulator layer, said contact opening being provided with an electrically conductive filling layer 214.

    摘要翻译： 在具有沟槽电容器1和选择晶体管2以及具有这种存储单元的半导体存储器的半导体衬底中制造动态存储单元的方法中，在选择晶体管和沟槽电容器之间形成介电绝缘体层17,201 ，选择晶体管的第一电极区域203基本上布置在沟槽电容器的块状内部电极102的上方，并且通过电介质绝缘体层中的接触开口213连接到所述电极，所述接触开口设置有电 导电填充层214。