公开(公告)号：US06590249B2

公开(公告)日：2003-07-08

申请号：US10166813

申请日：2002-06-11

申请人： Karl Heinz Küsters ,  Dietmar Temmler

发明人： Karl Heinz Küsters ,  Dietmar Temmler

IPC分类号： H01L27108

CPC分类号： H01L27/10867 ,  H01L27/10832 ,  H01L27/1203

摘要： In a method for fabricating a dynamic memory cell in a semiconductor substrate having a trench capacitor 1 and a selection transistor 2 and a semiconductor memory having such a memory cell, a dielectric insulator layer 17, 201 is formed between the selection transistor and the trench capacitor, a first electrode region 203 of the selection transistor essentially being arranged above a block-type inner electrode 102 of the trench capacitor and being connected to said electrode via a contact opening 213 in the dielectric insulator layer, said contact opening being provided with an electrically conductive filling layer 214.

摘要翻译： 在具有沟槽电容器1和选择晶体管2以及具有这种存储单元的半导体存储器的半导体衬底中制造动态存储单元的方法中，在选择晶体管和沟槽电容器之间形成介电绝缘体层17,201 ，选择晶体管的第一电极区域203基本上布置在沟槽电容器的块状内部电极102的上方，并且通过电介质绝缘体层中的接触开口213连接到所述电极，所述接触开口设置有电 导电填充层214。

公开(公告)号：US20060231918A1

公开(公告)日：2006-10-19

申请号：US10482328

申请日：2002-06-19

申请人： Martin Popp ,  Frank Richter ,  Dietmar Temmler ,  Andreas Wich-Glasen

发明人： Martin Popp ,  Frank Richter ,  Dietmar Temmler ,  Andreas Wich-Glasen

IPC分类号： H01L29/00

CPC分类号： H01L29/7851 ,  H01L21/76229 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/66651

摘要： A transistor is provided which advantageously utilizes a part of the area which, in conventional transistors, is provided for the isolation between the transistors. In this case, the channel width can be enlarged in a self-aligned manner without the risk of short circuits. The field-effect transistor according to the invention has the advantage that it is possible to ensure a significant increase in the effective channel width for the forward current ION compared with previously used, conventional transistor structures, without having to accept a reduction of the integration density that can be attained. Thus, by way of example, the forward current ION can be increased by up to 50%, without having to alter the arrangement of the active regions or of the trench isolation.

摘要翻译： 提供了一种晶体管，其有利地利用了在常规晶体管中提供用于晶体管之间的隔离的区域的一部分。 在这种情况下，可以以自对准的方式扩大通道宽度，而不会出现短路的风险。 根据本发明的场效应晶体管的优点在于，与先前使用的传统晶体管结构相比，可以确保正向电流ION的有效沟道宽度的显着增加，而不必接受集成密度的降低 可以实现。 因此，作为示例，正向电流I ON ON可以增加高达50％，而不必改变有源区域或沟槽隔离的布置。

公开(公告)号：US20060003560A1

公开(公告)日：2006-01-05

申请号：US11154943

申请日：2005-06-17

申请人： Jorn Regul ,  Dietmar Temmler

发明人： Jorn Regul ,  Dietmar Temmler

IPC分类号： H01L21/265 ,  H01L21/425 ,  H01L21/302

CPC分类号： H01L21/26586 ,  B81B2203/033 ,  B81B2203/0392 ,  B81C1/00404 ,  B81C2201/0159 ,  H01L21/32139 ,  H01L27/10867 ,  Y10S438/944

摘要： The present invention provides a method for fabricating a shadow mask in a trench of a microelectronic or micromechanical structure, comprising the steps of: providing a trench in the microelectronic or micromechanical structure; providing a partial filling in the trench; providing a first liner mask layer on the partial filling; providing a sacrificial filling on the liner mask layer to completely fill the trench; shallow etching back of the sacrificial filling into the trench; forming a first mask on the top side of the sacrificial filling in the trench; removing a subregion of the sacrificial filling in the trench using the first mask; and optionally removing a subregion of the first liner mask layer below it on the partial filling, the remaining subregion of the sacrificial filling in the trench serving as a second mask.

摘要翻译： 本发明提供了一种在微电子或微机械结构的沟槽中制造荫罩的方法，包括以下步骤：在微电子或微机械结构中提供沟槽; 提供在沟槽中的部分填充; 在部分填充上提供第一衬垫掩模层; 在衬垫掩模层上提供牺牲填充物以完全填充沟槽; 将蚀刻后的浅层刻蚀成沟槽; 在沟槽中的牺牲填充物的顶侧上形成第一掩模; 使用所述第一掩模去除所述沟槽中的牺牲填充的子区域; 并且可选地在部分填充上去除其下方的第一衬垫掩模层的子区域，在沟槽中牺牲填充的剩余子区域用作第二掩模。

公开(公告)号：US07535044B2

公开(公告)日：2009-05-19

申请号：US11700547

申请日：2007-01-31

申请人： Christoph Noelscher ,  Dietmar Temmler

发明人： Christoph Noelscher ,  Dietmar Temmler

IPC分类号： H01L27/108

CPC分类号： H01L21/764 ,  G03F1/36 ,  H01L27/0207 ,  H01L27/105

摘要： A semiconductor device with a substrate includes a structure. The structure has a first part and a second part. At least one section of the edge of the first part of the structure is at an essential constant distance measured parallel to the substrate to a first section of an edge of a second structure. At least one section of the edge of the second part of the structure is lined with an edge of a second section of the same second section. The first section of the edge of the second structure and a second section of the edge of the second structure merge at least at one point, whereby the angle between the tangents of the edges of the first and second section of the second structure is less than 90°. The structure and the second structure are distanced by a spacer structure.

摘要翻译： 具有衬底的半导体器件包括结构。 该结构具有第一部分和第二部分。 结构的第一部分的边缘的至少一个部分是平行于衬底测量到第二结构的边缘的第一部分的基本恒定距离。 结构的第二部分的边缘的至少一个部分衬有同一第二部分的第二部分的边缘。 第二结构的边缘的第一部分和第二结构的边缘的第二部分至少在一点处合并，由此第二结构的第一和第二部分的边缘的切线之间的角度小于 90°。 结构和第二结构由间隔结构隔开。

公开(公告)号：US07265025B2

公开(公告)日：2007-09-04

申请号：US11010186

申请日：2004-12-10

申请人： Dietmar Temmler ,  Barbara Lorenz ,  Daniel Koehler ,  Matthias Foerster

发明人： Dietmar Temmler ,  Barbara Lorenz ,  Daniel Koehler ,  Matthias Foerster

IPC分类号： H01L21/76

CPC分类号： H01L21/76877 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76865 ,  H01L27/10861 ,  H01L27/1087 ,  H01L28/60 ,  H01L28/84 ,  H01L29/66181

摘要： A method teaches how to fill trench structures formed in a semiconductor substrate. The trench structures are coated in a first deposition process with a first primary filling layer with a high conformity and minimal roughness. A V etching reaching down to a predetermined depth of the trench structure is subsequently performed in order to produce a V-profile.

摘要翻译： 一种方法教导了如何填充形成在半导体衬底中的沟槽结构。 沟槽结构在具有高一致性和最小粗糙度的第一初级填充层的第一沉积工艺中被涂覆。 随后进行达到沟槽结构的预定深度的V蚀刻，以便产生V形轮廓。

公开(公告)号：US07250336B2

公开(公告)日：2007-07-31

申请号：US11154943

申请日：2005-06-17

申请人： Jörn Regul ,  Dietmar Temmler

发明人： Jörn Regul ,  Dietmar Temmler

IPC分类号： H01L21/8242

CPC分类号： H01L21/26586 ,  B81B2203/033 ,  B81B2203/0392 ,  B81C1/00404 ,  B81C2201/0159 ,  H01L21/32139 ,  H01L27/10867 ,  Y10S438/944

摘要： The present invention provides a method for fabricating a shadow mask in a trench of a microelectronic or micromechanical structure, comprising the steps of: providing a trench in the microelectronic or micromechanical structure; providing a partial filling in the trench; providing a first liner mask layer on the partial filling; providing a sacrificial filling on the liner mask layer to completely fill the trench; shallow etching back of the sacrificial filling into the trench; forming a first mask on the top side of the sacrificial filling in the trench; removing a subregion of the sacrificial filling in the trench using the first mask; and optionally removing a subregion of the first liner mask layer below it on the partial filling, the remaining subregion of the sacrificial filling in the trench serving as a second mask.

摘要翻译： 本发明提供了一种在微电子或微机械结构的沟槽中制造荫罩的方法，包括以下步骤：在微电子或微机械结构中提供沟槽; 提供在沟槽中的部分填充; 在部分填充上提供第一衬垫掩模层; 在衬垫掩模层上提供牺牲填充物以完全填充沟槽; 将蚀刻后的浅层刻蚀成沟槽; 在沟槽中的牺牲填充物的顶侧上形成第一掩模; 使用所述第一掩模去除所述沟槽中的牺牲填充的子区域; 并且可选地在部分填充上去除其下方的第一衬垫掩模层的子区域，在沟槽中牺牲填充的剩余子区域用作第二掩模。

公开(公告)号：US07152461B2

公开(公告)日：2006-12-26

申请号：US11060571

申请日：2005-02-17

申请人： Dietmar Temmler ,  Peter Weidner

发明人： Dietmar Temmler ,  Peter Weidner

IPC分类号： G01B5/28

CPC分类号： G01B21/18 ,  G01G19/00 ,  G01N5/04

摘要： The invention relates to a method for determination of the depth of depressions which are formed in a mount substrate. According to the invention, an essentially uniform layer of a wetting agent is applied, which contains depressions, on a surface of the mount substrate, a time profile of the decrease in weight of the mount substrate is recorded, and the recorded time profile of the decrease in weight of the mount substrate is evaluated. The invention also relates to a measurement apparatus.

摘要翻译： 本发明涉及一种用于确定在安装基板中形成的凹陷深度的方法。 根据本发明，在安装基板的表面上施加基本上均匀的润湿剂层，其含有凹陷，记录安装基板的重量减小的时间曲线，记录时间曲线 评估安装基板的重量的减小。 本发明还涉及一种测量装置。

公开(公告)号：US20060134877A1

公开(公告)日：2006-06-22

申请号：US11285378

申请日：2005-11-23

申请人： Bernd Goebel ,  Dietmar Temmler ,  Arnd Scholz

发明人： Bernd Goebel ,  Dietmar Temmler ,  Arnd Scholz

IPC分类号： H01L29/94 ,  H01L21/20 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/10867

摘要： A buried conductive connection to a trench capacitor is formed in such a way that a contact area is provided between a conductive material layer which is arranged in the trench of the trench capacitor and contains a dopant and a semiconductor substrate between a first and a second predetermined trench depth, then dopant is outdiffused into the semiconductor substrate via the contact area by means of heating, in order to form the buried conductive connection in the semiconductor substrate, and afterward the conductive material layer containing the dopant is etched back into the trench as far as a third trench depth lying between the first and second predetermined trench depths, and the trench is covered with an insulation layer.

摘要翻译： 与沟槽电容器的埋入导电连接形成为使得接触区域设置在布置在沟槽电容器的沟槽中并且包含掺杂剂的导电材料层和在第一和第二预定的 沟槽深度，则通过加热，掺杂剂经由接触区域向外扩散到半导体衬底中，以便在半导体衬底中形成埋入的导电连接，之后将包含掺杂剂的导电材料层蚀刻回到沟槽中 作为位于第一和第二预定沟槽深度之间的第三沟槽深度，并且沟槽被绝缘层覆盖。

公开(公告)号：US20050090053A1

公开(公告)日：2005-04-28

申请号：US10501880

申请日：2003-01-08

申请人： Dietmar Temmler ,  Martin Gutsche ,  Martin Popp ,  Harald Seidl

发明人： Dietmar Temmler ,  Martin Gutsche ,  Martin Popp ,  Harald Seidl

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10867 ,  H01L27/10832 ,  H01L27/10864

摘要： Memory cells having trench capacitors, the trench capacitor being at least partially filled with a material which could not withstand high-temperature processes used during the fabrication of a memory chip without impairment of its electrical parameters. What is essential to the invention is that the material of the trench capacitor is introduced into the trench after the high-temperature processes. The method according to the invention makes it possible to use dielectric layers having large dielectric constants and electrode layers made of metallic material. The electrical properties of the trench capacitor are thus improved in comparison with known trench capacitors.

摘要翻译： 具有沟槽电容器的存储单元，沟槽电容器至少部分地填充有不能承受在制造存储器芯片期间使用的高温处理而不损害其电参数的材料。 本发明的重要内容是在高温处理之后将沟槽电容器的材料引入沟槽。 根据本发明的方法使得可以使用具有大介电常数的电介质层和由金属材料制成的电极层。 与已知的沟槽电容器相比，沟槽电容器的电性能得到改善。

公开(公告)号：US20080191257A1

公开(公告)日：2008-08-14

申请号：US11674164

申请日：2007-02-13

申请人： Dietmar Temmler ,  Alexander Sieck

发明人： Dietmar Temmler ,  Alexander Sieck

IPC分类号： H01L29/94 ,  H01L29/78

CPC分类号： H01L29/7834 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/7835 ,  H01L29/7854

摘要： A field-effect transistor includes a source region, a drain region and a channel region between the source and the drain region. A gate electrode is also arranged between them, where a lower edge of the gate electrode is formed below a lower edge of at least one of the source and drain regions. A first insulator structure is provided between the gate electrode and the source region. A second insulator structure is provided between the gate electrode and the drain region. The first and the second insulator structures are formed asymmetric and may be adapted to different requirements. The asymmetric approach may provide longer transistor channels, a lower resistance of the gate electrode and smaller footprints for 3D-channel-transistors of, for example, array and support transistors in memory cells or power applications.

摘要翻译： 场效应晶体管包括源极区，漏极区和源极和漏极区之间的沟道区。 栅极电极也布置在它们之间，其中栅电极的下边缘形成在源极和漏极区域中的至少一个的下边缘的下方。 在栅电极和源极区之间提供第一绝缘体结构。 在栅极电极和漏极区域之间提供第二绝缘体结构。 第一和第二绝缘体结构形成为不对称的并且可以适应于不同的要求。 非对称方法可以提供更长的晶体管通道，栅电极的较低电阻以及用于例如存储器单元或电力应用中的阵列和支持晶体管的3D通道晶体管的较小占位面积。