公开(公告)号：US07263002B2

公开(公告)日：2007-08-28

申请号：US11115298

申请日：2005-04-27

申请人： Kayoko Omoto

发明人： Kayoko Omoto

IPC分类号： G11C16/06

CPC分类号： G11C7/12 ,  G11C7/062 ,  G11C7/067 ,  G11C7/18 ,  G11C16/24 ,  G11C16/26

摘要： A plurality of first sub-bit lines are each connected to a common source line via a corresponding first sub-bit line reset transistor with NMOS structure, and a plurality of second sub-bit lines are each connected to the common source line via a corresponding second sub-bit line reset transistor with NMOS structure. The plurality of first and second sub-bit line reset transistors have their respective gates receiving a sub-bit line reset signal. This sub-bit line reset signal becomes “H” for a predetermined period of time after read data is obtained during a read period.

公开(公告)号：US07251165B2

公开(公告)日：2007-07-31

申请号：US10930873

申请日：2004-09-01

申请人： Yasuhiko Taito ,  Naoki Otani ,  Kayoko Omoto ,  Kenji Koda

发明人： Yasuhiko Taito ,  Naoki Otani ,  Kayoko Omoto ,  Kenji Koda

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/3495 ,  G11C16/3418 ,  G11C16/349

摘要： A semiconductor flash memory includes an erase/write control unit that, when performing an erase/write operation of read memory cells, reads and senses memory current of the read memory cells for each memory cell, and adjusts threshold voltage of each of the read memory cells to a predetermined value, and a readout control unit that, when performing a read operation, selects at least two read memory cells simultaneously from among the read memory cells to which the erase/write control unit stored the same data, and senses total memory current for the at least two read memory cells.

摘要翻译： 半导体闪速存储器包括擦除/写入控制单元，当执行读取存储器单元的擦除/写入操作时，读取和检测每个存储单元的读取的存储器单元的存储器电流，并且调整每个读取存储器的阈值电压 以及读出控制单元，当执行读取操作时，从擦除/写入控制单元存储相同数据的读取存储器单元中同时选择至少两个读取存储单元，并且感测总存储器 用于至少两个读存储器单元的电流。

公开(公告)号：US20070195601A1

公开(公告)日：2007-08-23

申请号：US11785561

申请日：2007-04-18

申请人： Kayoko Omoto

发明人： Kayoko Omoto

IPC分类号： G11C16/04

CPC分类号： G11C7/12 ,  G11C7/062 ,  G11C7/067 ,  G11C7/18 ,  G11C16/24 ,  G11C16/26

摘要： A plurality of first sub-bit lines are each connected to a common source line via a corresponding first sub-bit line reset transistor with NMOS structure, and a plurality of second sub-bit lines are each connected to the common source line via a corresponding second sub-bit line reset transistor with NMOS structure. The plurality of first and second sub-bit line reset transistors have their respective gates receiving a sub-bit line reset signal. This sub-bit line reset signal becomes “H” for a predetermined period of time after read data is obtained during a read period.

摘要翻译： 多个第一子位线分别经由具有NMOS结构的对应的第一子位线复位晶体管连接到公共源极线，并且多个第二子位线通过相应的第一子位线连接到公共源极线 具有NMOS结构的第二子位线复位晶体管。 多个第一和第二子位线复位晶体管的各自的栅极接收子位线复位信号。 在读取期间获得读取数据之后，该子位线复位信号在预定时间段内变为“H”。

公开(公告)号：US20050248985A1

公开(公告)日：2005-11-10

申请号：US11104602

申请日：2005-04-13

申请人： Kayoko Omoto

发明人： Kayoko Omoto

IPC分类号： G11C16/06 ,  G11C11/34 ,  G11C16/02 ,  G11C16/04 ,  G11C16/34

CPC分类号： G11C16/3436

摘要： In write/erase verity operations of a memory transistor in a semiconductor memory, control of the semiconductor memory follows the following process. One main bit line is applied to be operative on the select side and another main bit line is applied to be operative on the reference side. On the select side, a sub bit line select transistor is turned on to select a sub bit line having connection to the memory transistor as a target for write/erase verify operations. The target memory transistor is turned on while the other memory transistors connected to the same sub bit line are turned off. On the reference side, a sub bit line select transistor is turned off to bring a sub bit line to a non-selected state.

摘要翻译： 在半导体存储器中的存储晶体管的写入/擦除验证操作中，半导体存储器的控制遵循以下处理。 一个主位线被应用于在选择侧操作，另一个主位线被应用于在参考侧上操作。 在选择侧，子位线选择晶体管导通以选择具有与存储晶体管连接的子位线作为写入/擦除验证操作的目标。 目标存储晶体管导通，而连接到同一子位线的其它存储晶体管截止。 在参考侧，子位线选择晶体管截止，使子位线处于非选择状态。

公开(公告)号：US07428174B2

公开(公告)日：2008-09-23

申请号：US11736129

申请日：2007-04-17

申请人： Yasuhiko Taito ,  Naoki Otani ,  Kayoko Omoto ,  Kenji Koda

发明人： Yasuhiko Taito ,  Naoki Otani ,  Kayoko Omoto ,  Kenji Koda

IPC分类号： G11C11/34

CPC分类号： G11C16/3495 ,  G11C16/3418 ,  G11C16/349

摘要： A semiconductor flash memory includes an erase/write control unit that, when performing an erase/write operation of read memory cells, reads and senses memory current of the read memory cells for each memory cell, and adjusts threshold voltage of each of the read memory cells to a predetermined value, and a readout control unit that, when performing a read operation, selects at least two read memory cells simultaneously from among the read memory cells to which the erase/write control unit stored the same data, and senses total memory current for the at least two read memory cells.

公开(公告)号：US20070242521A1

公开(公告)日：2007-10-18

申请号：US11766133

申请日：2007-06-21

申请人： Yasuhiko Taito ,  Naoki Otani ,  Kayoko Omoto ,  Kenji Koda

发明人： Yasuhiko Taito ,  Naoki Otani ,  Kayoko Omoto ,  Kenji Koda

IPC分类号： G11C16/08

CPC分类号： G11C16/3495 ,  G11C16/3418 ,  G11C16/349

摘要： A semiconductor flash memory includes an erase/write control unit that, when performing an erase/write operation of read memory cells, reads and senses memory current of the read memory cells for each memory cell, and adjusts threshold voltage of each of the read memory cells to a predetermined value, and a readout control unit that, when performing a read operation, selects at least two read memory cells simultaneously from among the read memory cells to which the erase/write control unit stored the same data, and senses total memory current for the at least two read memory cells.

摘要翻译： 半导体闪速存储器包括擦除/写入控制单元，当执行读取存储器单元的擦除/写入操作时，读取和检测每个存储单元的读取的存储器单元的存储器电流，并且调整每个读取存储器的阈值电压 以及读出控制单元，当执行读取操作时，从擦除/写入控制单元存储相同数据的读取存储器单元中同时选择至少两个读取存储单元，并且感测总存储器 用于至少两个读存储器单元的电流。

公开(公告)号：US20070189078A1

公开(公告)日：2007-08-16

申请号：US11736129

申请日：2007-04-17

申请人： Yasuhiko TAITO ,  Naoki OTANI ,  Kayoko OMOTO ,  Kenji KODA

发明人： Yasuhiko TAITO ,  Naoki OTANI ,  Kayoko OMOTO ,  Kenji KODA

IPC分类号： G11C16/04

CPC分类号： G11C16/3495 ,  G11C16/3418 ,  G11C16/349

摘要： A semiconductor flash memory includes an erase/write control unit that, when performing an erase/write operation of read memory cells, reads and senses memory current of the read memory cells for each memory cell, and adjusts threshold voltage of each of the read memory cells to a predetermined value, and a readout control unit that, when performing a read operation, selects at least two read memory cell simultaneously from among the read memory cells to which the erase/write control unit stored the same data, and senses total memory current for the at least two read memory cells

摘要翻译： 半导体闪速存储器包括擦除/写入控制单元，当执行读取存储器单元的擦除/写入操作时，读取和检测每个存储单元的读取的存储器单元的存储器电流，并且调整每个读取存储器的阈值电压 单元到预定值，以及读出控制单元，当执行读取操作时，从擦除/写入控制单元存储相同数据的读取存储器单元中同时选择至少两个读取存储单元，并且感测总存储器 用于至少两个读存储器单元的电流

公开(公告)号：US20050243622A1

公开(公告)日：2005-11-03

申请号：US11115298

申请日：2005-04-27

申请人： Kayoko Omoto

发明人： Kayoko Omoto

IPC分类号： G11C16/06 ,  G11C7/06 ,  G11C7/12 ,  G11C7/18 ,  G11C11/34 ,  G11C16/24 ,  G11C16/26

CPC分类号： G11C7/12 ,  G11C7/062 ,  G11C7/067 ,  G11C7/18 ,  G11C16/24 ,  G11C16/26

摘要： A plurality of first sub-bit lines are each connected to a common source line via a corresponding first sub-bit line reset transistor with NMOS structure, and a plurality of second sub-bit lines are each connected to the common source line via a corresponding second sub-bit line reset transistor with NMOS structure. The plurality of first and second sub-bit line reset transistors have their respective gates receiving a sub-bit line reset signal. This sub-bit line reset signal becomes “H” for a predetermined period of time after read data is obtained during a read period.

摘要翻译： 多个第一子位线分别经由具有NMOS结构的对应的第一子位线复位晶体管连接到公共源极线，并且多个第二子位线通过相应的第一子位线连接到公共源极线 具有NMOS结构的第二子位线复位晶体管。 多个第一和第二子位线复位晶体管的各自的栅极接收子位线复位信号。 在读取期间获得读取数据之后，该子位线复位信号在预定时间段内变为“H”。

公开(公告)号：US20050057972A1

公开(公告)日：2005-03-17

申请号：US10930873

申请日：2004-09-01

申请人： Yasuhiko Taito ,  Naoki Otani ,  Kayoko Omoto ,  Kenji Koda

发明人： Yasuhiko Taito ,  Naoki Otani ,  Kayoko Omoto ,  Kenji Koda

IPC分类号： G11C16/02 ,  G11C16/06 ,  G11C16/34 ,  G11C11/34

CPC分类号： G11C16/3495 ,  G11C16/3418 ,  G11C16/349

摘要： A semiconductor flash memory includes an erase/write control unit that, when performing an erase/write operation of read memory cells, reads and senses memory current of the read memory cells for each memory cell, and adjusts threshold voltage of each of the read memory cells to a predetermined value, and a readout control unit that, when performing a read operation, selects at least two read memory cells simultaneously from among the read memory cells to which the erase/write control unit stored the same data, and senses total memory current for the at least two read memory cells.

摘要翻译： 半导体闪速存储器包括擦除/写入控制单元，当执行读取存储器单元的擦除/写入操作时，读取和检测每个存储单元的读取的存储器单元的存储器电流，并且调整每个读取存储器的阈值电压 以及读出控制单元，当执行读取操作时，从擦除/写入控制单元存储相同数据的读取存储器单元中同时选择至少两个读取存储单元，并且感测总存储器 用于至少两个读存储器单元的电流。

公开(公告)号：US06538930B2

公开(公告)日：2003-03-25

申请号：US09972895

申请日：2001-10-10

申请人： Motoharu Ishii ,  Kayoko Omoto

发明人： Motoharu Ishii ,  Kayoko Omoto

IPC分类号： G11C514

CPC分类号： G11C16/30 ,  G11C5/145

摘要： A charge pump circuit comprising: a first reverse current prevention circuit connected between an external power supply and a first internal node; a first output node, connected to the first internal node, for outputting a first output potential; a second reverse current prevention circuit connected between a second power supply node receiving ground potential and a second internal node; and power supply generation circuit, connected between the first internal node and second internal node, for enhancing the potential of the second internal node as compared to that of the first internal node, wherein the power supply generation circuit is formed on or within a semiconductor substrate, and includes a diode element provided so as to flow a current from the first internal node to the second internal node, and a capacitor having one electrode connected to the first and second nodes, and the other electrode provided with a clock signal, thereby enabling higher outputs on both positive and negative voltages.

摘要翻译： 一种电荷泵电路，包括：连接在外部电源和第一内部节点之间的第一反向电流防止电路; 连接到第一内部节点的第一输出节点，用于输出第一输出电位; 连接在接收地电位的第二电源节点和第二内部节点之间的第二反向电流防止电路; 以及连接在所述第一内部节点和所述第二内部节点之间的电源产生电路，用于与所述第一内部节点相比增强所述第二内部节点的电位，其中所述电源产生电路形成在半导体衬底上或其内部 并且包括设置成使电流从第一内部节点流动到第二内部节点的二极管元件，以及具有连接到第一和第二节点的一个电极的电容器，以及设置有时钟信号的另一个电极，从而使能 正电压和负电压都有较高的输出。