公开(公告)号：US20050032327A1

公开(公告)日：2005-02-10

申请号：US10936684

申请日：2004-09-09

申请人： Kazuhiro Ohnishi ,  Nobuyuki Sugii ,  Takahiro Onai

发明人： Kazuhiro Ohnishi ,  Nobuyuki Sugii ,  Takahiro Onai

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L21/336

CPC分类号： H01L29/1054 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/7833

摘要： A method and device are provided for shallow trench isolation for a silicon wafer containing silicon-germanium. In one example, the method comprises forming a trench region in a silicon-germanium layer of a semiconductor substrate containing a single crystal silicon-germanium layer on the surface; forming a first single crystal silicon layer in the trench region and an active region; oxidizing the first single crystal silicon layer; forming a first thermal oxide layer on the surface of the first single crystal silicon layer; forming a device isolation region; embedding an insulator in the trench region; and forming a device in an active region over the single crystal silicon-germanium layer separated by the device isolation region, wherein the step of forming the device in the active region further includes forming a doped region of a depth to reach within the single crystal silicon-germanium layer below the first single crystal silicon layer.

公开(公告)号：US06835632B2

公开(公告)日：2004-12-28

申请号：US10460215

申请日：2003-06-13

申请人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

发明人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

IPC分类号： H01L2120

CPC分类号： H01L27/0652 ,  H01L27/0688 ,  H01L28/20

摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

摘要翻译： 本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。 使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且第一多晶硅层具有正的温度对电阻的依赖性，而第二多晶硅层的第二 多晶硅层具有负电阻的温度依赖性，反之亦然。 此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

公开(公告)号：US06524924B1

公开(公告)日：2003-02-25

申请号：US09123406

申请日：1998-07-28

申请人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

发明人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

IPC分类号： H01L2120

CPC分类号： H01L27/0652 ,  H01L27/0688 ,  H01L28/20

摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistances while the second polycrystalline layer has a negative temperature dependance of resistance, or vise versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

摘要翻译： 本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。 使用包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的至少两层结构，并且第一多晶硅层具有正电温度依赖性而第二 多晶层具有电阻的负温度依赖性，反之亦然。 此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

公开(公告)号：US20090034143A1

公开(公告)日：2009-02-05

申请号：US11574052

申请日：2005-08-24

申请人： Kazuhiro Ohnishi

发明人： Kazuhiro Ohnishi

IPC分类号： H02H9/06

CPC分类号： H01L29/885 ,  H01L27/0255

摘要： A semiconductor device for surge protection having high surge resistance is provided. A semiconductor substrate (10) included in the semiconductor device for surge protection according to the present invention includes a high concentration first conductivity type semiconductor substrate (1), a low concentration first conductivity type semiconductor layer (2), a high concentration first conductivity type semiconductor layer (4), a second conductivity type semiconductor layer (3), and a cylindrical low concentration second conductivity type semiconductor layer (5) that extends from a surface of the low concentration first conductivity type semiconductor layer (2) into the low concentration first conductivity type semiconductor layer (2) so as to share an axis with the high concentration first conductivity type semiconductor layer (4), and has an interface (J4) with the high concentration first conductivity type semiconductor layer (4) and an interface (J5) with the second conductivity type semiconductor layer (3). Further, the low concentration second conductivity type semiconductor layer (5) has an impurity concentration lower than an impurity concentration of the second conductivity type semiconductor layer (3).

摘要翻译： 提供了具有高浪涌电阻的浪涌保护的半导体器件。 根据本发明的用于电涌保护的半导体器件中包括的半导体衬底（10）包括高浓度第一导电类型半导体衬底（1），低浓度第一导电类型半导体层（2），高浓度第一导电类型 半导体层（4），第二导电型半导体层（3）和从低浓度第一导电类型半导体层（2）的表面延伸到低浓度的圆筒形低浓度第二导电型半导体层（5） 第一导电型半导体层（2），以与高浓度第一导电类型半导体层（4）共轴，并且具有与高浓度第一导电类型半导体层（4）和界面（J4）的界面 J5）与第二导电型半导体层（3）。 此外，低浓度第二导电型半导体层（5）的杂质浓度低于第二导电型半导体层（3）的杂质浓度。

公开(公告)号：US07238582B2

公开(公告)日：2007-07-03

申请号：US11000092

申请日：2004-12-01

申请人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

发明人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

IPC分类号： H01L21/8222

CPC分类号： H01L27/0652 ,  H01L27/0688 ,  H01L28/20

摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

摘要翻译： 本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。 使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且第一多晶硅层具有正的温度对电阻的依赖性，而第二多晶硅层的第二 多晶硅层具有负电阻的温度依赖性，反之亦然。 此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

公开(公告)号：US20050173738A1

公开(公告)日：2005-08-11

申请号：US11049998

申请日：2005-02-04

申请人： Masao Kondo ,  Yutaka Hoshino ,  Kazuhiro Ohnishi ,  Isao Yoshida ,  Masatoshi Morikawa

发明人： Masao Kondo ,  Yutaka Hoshino ,  Kazuhiro Ohnishi ,  Isao Yoshida ,  Masatoshi Morikawa

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L29/45 ,  H01L29/80

CPC分类号： H01L29/66659 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0886 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/456 ,  H01L29/66628 ,  H01L29/7835 ,  H01L29/7842

摘要： Provided is a technology capable of reducing the on-resistance of a power MISFET while suppressing the generation of defects in a strained silicon layer. A strained silicon layer is formed only over an underlying strained silicon layer in the drain region by epitaxial growth. Large portions of a lightly-doped n type impurity diffusion region, offset region and heavily-doped n type impurity diffusion region are formed in these strained silicon layers, having a higher electron mobility than a conventional silicon layer.

摘要翻译： 提供了一种能够在抑制应变硅层中的缺陷的产生的同时降低功率MISFET的导通电阻的技术。 通过外延生长仅在漏极区域中的下层应变硅层上形成应变硅层。 在这些应变硅层中形成大量的轻掺杂n型杂质扩散区域，偏移区域和重掺杂n型杂质扩散区域，其具有比常规硅层更高的电子迁移率。

公开(公告)号：US08004041B2

公开(公告)日：2011-08-23

申请号：US11574052

申请日：2005-08-24

申请人： Kazuhiro Ohnishi

发明人： Kazuhiro Ohnishi

IPC分类号： H01L23/62 ,  H01L29/861 ,  H01L31/107

CPC分类号： H01L29/885 ,  H01L27/0255

摘要： A semiconductor device for surge protection having high surge resistance is provided. A semiconductor substrate (10) included in the semiconductor device for surge protection according to the present invention includes a high concentration first conductivity type semiconductor substrate (1), a low concentration first conductivity type semiconductor layer (2), a high concentration first conductivity type semiconductor layer (4), a second conductivity type semiconductor layer (3), and a cylindrical low concentration second conductivity type semiconductor layer (5) that extends from a surface of the low concentration first conductivity type semiconductor layer (2) into the low concentration first conductivity type semiconductor layer (2) so as to share an axis with the high concentration first conductivity type semiconductor layer (4), and has an interface (J4) with the high concentration first conductivity type semiconductor layer (4) and an interface (J5) with the second conductivity type semiconductor layer (3). Further, the low concentration second conductivity type semiconductor layer (5) has an impurity concentration lower than an impurity concentration of the second conductivity type semiconductor layer (3).

摘要翻译： 提供了具有高浪涌电阻的浪涌保护的半导体器件。 根据本发明的用于电涌保护的半导体器件中包括的半导体衬底（10）包括高浓度第一导电类型半导体衬底（1），低浓度第一导电类型半导体层（2），高浓度第一导电类型 半导体层（4），第二导电型半导体层（3）和从低浓度第一导电类型半导体层（2）的表面延伸到低浓度的圆筒形低浓度第二导电型半导体层（5） 第一导电型半导体层（2），以与高浓度第一导电类型半导体层（4）共轴，并且具有与高浓度第一导电类型半导体层（4）和界面（J4）的界面 J5）与第二导电型半导体层（3）。 此外，低浓度第二导电型半导体层（5）的杂质浓度低于第二导电型半导体层（3）的杂质浓度。

公开(公告)号：US06936875B2

公开(公告)日：2005-08-30

申请号：US10673789

申请日：2003-09-30

申请人： Nobuyuki Sugii ,  Kazuhiro Ohnishi ,  Katsuyoshi Washio

发明人： Nobuyuki Sugii ,  Kazuhiro Ohnishi ,  Katsuyoshi Washio

IPC分类号： H01L21/764 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/10 ,  H01L29/786 ,  H01L29/80

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/78648 ,  H01L29/78687 ,  H01L29/802

摘要： With the invention, it is possible to avoid deterioration in short-channel characteristics, caused by a silicon germanium layer coming into contact with the channel of a strained SOI transistor. Further, it is possible to fabricate a double-gate type of strained SOI transistor or to implement mixedly mounting the strained SOI transistor and a conventional silicon or SOI transistor on the same wafer. According to the invention, for example, a strained silicon layer is grown on a strain-relaxed silicon germanium layer, and subsequently, portions of the silicon germanium layer are removed, thereby constituting a channel layer in the strained silicon layer.

摘要翻译： 利用本发明，可以避免由与应变SOI晶体管的沟道接触的硅锗层引起的短沟道特性的劣化。 此外，可以制造双栅型应变SOI晶体管，或者在同一晶片上实现将应变SOI晶体管和常规硅或SOI晶体管混合安装。 根据本发明，例如，在应变松弛硅锗层上生长应变硅层，随后去除硅锗层的部分，从而在应变硅层中构成沟道层。

公开(公告)号：US20050164441A1

公开(公告)日：2005-07-28

申请号：US11087612

申请日：2005-03-24

申请人： Kazuhiro Ohnishi ,  Naoki Yamamoto

发明人： Kazuhiro Ohnishi ,  Naoki Yamamoto

IPC分类号： H01L21/28 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/4941 ,  H01L21/28052 ,  H01L21/76229 ,  H01L21/823835 ,  H01L21/823842

摘要： Process for producing a semiconductor device includes forming an insulation layer on a semiconductor substrate surface and depositing a silicon layer on the insulation layer, a reaction barrier layer such as a metal nitride layer on the first metallic layer and a second metallic layer on the barrier layer, processing a stacked structure of the silicon layer, first metallic layer, barrier layer and second metallic layer to form a gate electrode, using the gate electrode as a mask and doping an impurity into the surface of the semiconductor substrate to form active regions of the device, heat reacting the first metallic layer with the silicon layer to form a metal silicide layer between the reaction barrier layer and the silicon layer. The heat reaction process effected may be performed prior to or after the formation of the gate electrode. The metal silicide film may be a deposited film.

摘要翻译： 制造半导体器件的方法包括在半导体衬底表面上形成绝缘层并在绝缘层上沉积硅层，在第一金属层上形成诸如金属氮化物层的反应势垒层和阻挡层上的第二金属层 处理硅层，第一金属层，阻挡层和第二金属层的堆叠结构以形成栅电极，使用栅电极作为掩模，并将杂质掺杂到半导体衬底的表面中以形成有源区 使第一金属层与硅层热反应，以在反应阻挡层和硅层之间形成金属硅化物层。 所产生的热反应过程可以在形成栅电极之前或之后进行。 金属硅化物膜可以是沉积膜。

公开(公告)号：US20050101097A1

公开(公告)日：2005-05-12

申请号：US11000092

申请日：2004-12-01

申请人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

发明人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

IPC分类号： H01C7/06 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H01L21/20 ,  H01L21/8222

CPC分类号： H01L27/0652 ,  H01L27/0688 ,  H01L28/20

摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

摘要翻译： 本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。 使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且第一多晶硅层具有正的温度对电阻的依赖性，而第二多晶硅层的第二 多晶硅层具有负电阻的温度依赖性，反之亦然。 此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。