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公开(公告)号：US20080301376A1
公开(公告)日：2008-12-04
申请号：US11756039
申请日：2007-05-31
IPC分类号： G06F12/00
CPC分类号： G06F12/0817
摘要： A memory controller receives a stream of DMA write operations and enqueues them in a queue enforcing a First-In First-Out (FIFO) order. Prior to processing a particular DMA write operation, the memory controller acquires coherency ownership of a target memory block and stores the result in a low latency array. In response to acquiring coherency ownership, this low latency array is updated to a coherency state signifying coherency ownership by the memory controller. In a pipelined array access, both the low latency array and the second array are accessed and if the lower latency second array indicates the particular coherency state with no collision indication, the memory controller signals that the particular DMA write operation can be performed, where the signaling occurs prior to results being obtained from the higher latency first array at the normal end of the array access pipeline. In response to the signaling, the memory controller performs an update to the memory subsystem indicated by the particular DMA write operation.
摘要翻译： 存储器控制器接收DMA写操作流并将其排入队列中，执行先进先出（FIFO）顺序。 在处理特定DMA写入操作之前，存储器控制器获取目标存储器块的一致性所有权并将结果存储在低延迟数组中。 响应于获取一致性所有权，该低延迟阵列被更新为表示存储器控制器的一致性所有权的一致性状态。 在流水线阵列访问中，访问低延迟阵列和第二阵列，并且如果较低等待时间的第二阵列指示没有冲突指示的特定一致性状态，则存储器控制器指示可以执行特定的DMA写操作，其中 信号发生在从阵列访问管道的正常端的较高等待时间第一阵列获得的结果之前。 响应于信令，存储器控制器对由特定DMA写操作指示的存储器子系统进行更新。
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2.发明申请Memory Controller and Method for Multi-Path Address Translation in Non-Uniform Memory Configurations 失效内存控制器和非均匀内存配置中多路径地址转换的方法公开(公告)号：US20090119478A1
公开(公告)日：2009-05-07
申请号：US11934974
申请日：2007-11-05
IPC分类号： G06F9/34
CPC分类号： G06F12/0292 , G06F12/0607
摘要： In a method of translating a physical memory address to a device address in a device memory space, a fast address translate of the physical memory address, adapted to translate addresses in uniformly configured device memory space, is performed thereby generating a first translated address. A full address translate of the physical memory address, adapted to translate addresses in non-uniformly configured device memory space, is also performed thereby generating a second translated address. Boundaries of a uniform portion of the device memory space are identified, to which the physical memory address is compared to determine if the physical memory address is in the uniform portion of the device memory space. When the physical memory address is in the uniform portion, the first translated address is selected as the device address. Otherwise, the second translated address is selected.
摘要翻译： 在将物理存储器地址转换为设备存储器空间中的设备地址的方法中，执行适于在统一配置的设备存储器空间中翻译地址的物理存储器地址的快速地址转换，从而生成第一翻译地址。 物理存储器地址的完整地址转换也适用于在非均匀配置的设备存储器空间中翻译地址，从而生成第二翻译地址。 识别设备存储器空间的统一部分的边界，与物理存储器地址进行比较以确定物理存储器地址是否在设备存储器空间的统一部分中。 当物理存储器地址在均匀部分中时，第一个翻译地址被选择为设备地址。 否则，选择第二个翻译的地址。
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3.发明申请Method, Apparatus, System and Program Product Supporting Directory-Assisted Speculative Snoop Probe With Concurrent Memory Access 审中-公开方法，设备，系统和程序产品支持目录辅助的具有并发存储器访问的投机窥探探测器公开(公告)号：US20080244189A1
公开(公告)日：2008-10-02
申请号：US11693809
申请日：2007-03-30
申请人： Brian D. Allison , Wayne M. Barrett , Philip R. Hillier , Kenneth M. Valk , Brian T. Vanderpool
发明人： Brian D. Allison , Wayne M. Barrett , Philip R. Hillier , Kenneth M. Valk , Brian T. Vanderpool
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F12/0882 , G06F2212/507
摘要： A multiprocessor data processing system includes a memory controller controlling access to a memory subsystem, multiple processor buses coupled to the memory controller, and at least one of multiple processors coupled to each processor bus. In response to receiving a first read request of a first processor via a first processor bus, the memory controller initiates a speculative access to the memory subsystem and a lookup of the target address in a central coherence directory. In response to the central coherence directory indicating that a copy of the target memory block is cached by a second processor, the memory controller transmits a second read request for the target address on a second processor bus. In response to receiving a clean snoop response to the second read request, the memory controller provides to the first processor the target memory block retrieved from the memory subsystem by the speculative access.
摘要翻译： 多处理器数据处理系统包括控制对存储器子系统的访问的存储器控制器，耦合到存储器控制器的多个处理器总线以及耦合到每个处理器总线的多个处理器中的至少一个。 响应于经由第一处理器总线接收到第一处理器的第一读取请求，存储器控制器启动对存储器子系统的推测访问以及在中央一致性目录中查找目标地址。 响应于指示目标存储器块的副本被第二处理器缓存的中央一致性目录，存储器控制器在第二处理器总线上发送针对目标地址的第二读取请求。 响应于对第二读取请求接收到干净的窥探响应，存储器控制器通过投机访问向第一处理器提供从存储器子系统检索的目标存储器块。
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4.发明申请公开(公告)号：US20090271532A1
公开(公告)日：2009-10-29
申请号：US12108744
申请日：2008-04-24
IPC分类号： G06F13/14
CPC分类号： G06F11/1004
摘要： A method is provided for processing a command issued by a processor over a bus. The method includes (1) transmitting the command to a remote node to obtain access to data required to complete the command; (2) receiving from the remote node a response packet including a header and a header CRC; (3) validating the response packet including the header and the header CRC; (4) loading a timer to run until data required to complete the command is received or the timer expires; and (5) before receiving the data required to complete the command, arranging to return the data to the processor over the bus.
摘要翻译： 提供了一种用于处理由总线发出的处理器的命令的方法。 该方法包括（1）将命令发送到远程节点以获得完成命令所需的数据; （2）从远程节点接收包括报头和报头CRC的响应分组; （3）验证包括报头和报头CRC的响应报文; （4）加载定时器运行，直到接收完成命令所需的数据或定时器到期; 和（5）在接收完成命令所需的数据之前，安排通过总线将数据返回给处理器。
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5.发明授权Memory controller and method for multi-path address translation in non-uniform memory configurations 失效用于非均匀内存配置中多路径地址转换的内存控制器和方法公开(公告)号：US07793034B2
公开(公告)日：2010-09-07
申请号：US11934974
申请日：2007-11-05
IPC分类号： G06F12/00
CPC分类号： G06F12/0292 , G06F12/0607
摘要： In a method of translating a physical memory address to a device address in a device memory space, a fast address translate of the physical memory address, adapted to translate addresses in uniformly configured device memory space, is performed thereby generating a first translated address. A full address translate of the physical memory address, adapted to translate addresses in non-uniformly configured device memory space, is also performed thereby generating a second translated address. Boundaries of a uniform portion of the device memory space are identified, to which the physical memory address is compared to determine if the physical memory address is in the uniform portion of the device memory space. When the physical memory address is in the uniform portion, the first translated address is selected as the device address. Otherwise, the second translated address is selected.
摘要翻译： 在将物理存储器地址转换为设备存储器空间中的设备地址的方法中，执行适于在统一配置的设备存储器空间中翻译地址的物理存储器地址的快速地址转换，从而生成第一翻译地址。 物理存储器地址的完整地址转换也适用于在非均匀配置的设备存储器空间中翻译地址，从而生成第二翻译地址。 识别设备存储器空间的统一部分的边界，与物理存储器地址进行比较以确定物理存储器地址是否在设备存储器空间的统一部分中。 当物理存储器地址在均匀部分中时，第一个翻译地址被选择为设备地址。 否则，选择第二个翻译的地址。
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公开(公告)号：US07694055B2
公开(公告)日：2010-04-06
申请号：US11251334
申请日：2005-10-15
申请人： Ryuji Orita , Susumu Arai , Brian D. Allison , Patrick M. Bland
发明人： Ryuji Orita , Susumu Arai , Brian D. Allison , Patrick M. Bland
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： Interrupts are directed to currently idle processors. Which of a number of processors of a computing system that are currently idle is determined. An interrupt is received and directed to one of the currently idle processors for processing. Determining which processors are currently idle can be accomplished by monitoring each processor to determine whether it has entered an idle state. When a processor has entered an idle state, it is thus determined that the processor is currently idle. Where just one processor is currently idle, an interrupt is directed to this processor. Where more than one processor is currently idle, one of these processors is selected to which to deliver an interrupt, such as in a round-robin manner. Where no processor is currently idle, then one of the processors is selected to which to deliver an interrupt.
摘要翻译： 中断针对当前空闲的处理器。 确定当前空闲的计算系统的多个处理器中的哪一个。 接收到中断并将其定向到当前空闲处理器之一进行处理。 确定哪些处理器当前处于空闲状态可以通过监视每个处理器来确定它是否进入空闲状态。 当处理器进入空闲状态时，因此确定处理器当前处于空闲状态。 当一个处理器当前处于空闲状态时，一个中断就被指向这个处理器。 当多个处理器当前空闲时，选择这些处理器之一来传送中断，例如以循环方式。 在没有处理器当前空闲的情况下，选择一个处理器来传送中断。
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7.发明申请System Performance Through Invalidation of Speculative Memory Scrub Commands 审中-公开通过推测内存清理命令无效的系统性能公开(公告)号：US20090307523A1
公开(公告)日：2009-12-10
申请号：US12134397
申请日：2008-06-06
CPC分类号： G06F11/106 , G06F9/3004 , G06F9/30047
摘要： A memory controller and a method for improved computer system performance invalidates (i.e., cancels or does not allow for execution of) speculative or unnecessary scrub write commands as part of the periodic execution of the overall scrub command upon the occurrence of certain events, such as if the error checking and correction (ECC) operation indicates that the data were received without error or if the ECC operation indicates that the data received have an uncorrectable error.
摘要翻译： 存储器控制器和用于改进的计算机系统性能的方法在某些事件发生时使得整体擦除命令的周期性执行的一部分使得推测性或不必要的擦写写命令无效（例如，取消或不允许执行），例如 如果错误检查和校正（ECC）操作指示数据被接收到没有错误或者ECC操作指示接收的数据具有不可校正的错误。
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8.发明申请公开(公告)号：US20090268736A1
公开(公告)日：2009-10-29
申请号：US12108637
申请日：2008-04-24
IPC分类号： H04L12/56
CPC分类号： H04L1/0061 , H04L1/0072 , H04L2001/0094
摘要： A method is provided for processing commands issued by a processor over a bus. The method includes the steps of (1) transmitting the command to a remote node to obtain access to data required to complete the command; (2) receiving from the remote node a response packet including a header and a header CRC; (3) validating the response packet based on the header CRC; and (4) before receiving the data required to complete the command, arranging to return the data to the processor over the bus.
摘要翻译： 提供了一种处理由总线发出的命令的方法。 该方法包括以下步骤：（1）将命令发送到远程节点以获得对完成命令所需的数据的访问; （2）从远程节点接收包括报头和报头CRC的响应分组; （3）基于报头CRC验证响应分组; 和（4）在接收完成命令所需的数据之前，安排通过总线将数据返回到处理器。
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9.发明申请公开(公告)号：US20090268727A1
公开(公告)日：2009-10-29
申请号：US12108735
申请日：2008-04-24
IPC分类号： H04L12/56
CPC分类号： H04L69/22 , H04L69/324
摘要： A method is provided for processing a command issued by a processor over a bus. The method includes (1) transmitting the command to a remote node to obtain access to data required to complete the command; (2) receiving from the remote node a response packet including a header and a variable gap; and (3) before receiving the data required to complete the command, arranging to return the data to the processor over the bus.
摘要翻译： 提供了一种用于处理由总线发出的处理器的命令的方法。 该方法包括（1）将命令发送到远程节点以获得完成命令所需的数据; （2）从远程节点接收包括报头和可变间隙的响应分组; 和（3）在接收完成命令所需的数据之前，安排通过总线将数据返回到处理器。
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