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    METHODS AND CIRCUITS FOR ATTENUATING HIGH-FREQUENCY NOISE
    1.
    发明申请
    METHODS AND CIRCUITS FOR ATTENUATING HIGH-FREQUENCY NOISE 审中-公开
    降低高频噪声的方法和电路

    公开(公告)号：US20130049884A1

    公开(公告)日：2013-02-28

    申请号：US13214749

    申请日：2011-08-22

    申请人： Kevin Patrick Lavery ,  Pravin P. Patel

    发明人： Kevin Patrick Lavery ,  Pravin P. Patel

    IPC分类号： H03H7/00

    CPC分类号： H03H11/1213 ,  H03K19/00361

    摘要： Low-frequency digital data input signals in an integrated circuit are controlled between first and second stages in a signal input path of the integrated circuit by a capacitance in the signal input path between the first and second stages. The capacitance is sized to attenuate high-frequency noise in the signal input path. In one embodiment, the integrated circuit may be an input buffer circuit in which the capacitance is a capacitor between the signal input path and a reference potential, a voltage source, or both. In another embodiment, the integrated circuit may be an oscillator circuit in which the capacitance is provided between corresponding elements of a differential pair of transistors in the first stage.

    摘要翻译： 集成电路中的低频数字数据输入信号通过第一和第二级之间的信号输入路径中的电容在集成电路的信号输入路径中的第一和第二级之间进行控制。 电容的大小可以衰减信号输入路径中的高频噪声。 在一个实施例中，集成电路可以是输入缓冲器电路，其中电容是信号输入路径和参考电位之间的电容器，电压源或两者。 在另一个实施例中，集成电路可以是其中电容被提供在第一级中的差分晶体管对的元件之间的振荡器电路。

    Watch-Dog Timer with Support for Multiple Masters
    2.
    发明申请
    Watch-Dog Timer with Support for Multiple Masters 有权
    看门狗定时器，支持多个主控

    公开(公告)号：US20120110388A1

    公开(公告)日：2012-05-03

    申请号：US12939085

    申请日：2010-11-03

    申请人： Kevin Patrick Lavery

    发明人： Kevin Patrick Lavery

    IPC分类号： G06F11/30

    CPC分类号： G06F11/0757 ,  G06F11/0721

    摘要： A time-out period is established for a watchdog timer. The time-out period is restarted each time a designated key value is received when each key value is received in a proper sequence. An error is indicated if set of key values is received in an incorrect sequence. A time-out is indicated if a correct sequence of key values is not received within the time-out period.

    摘要翻译： 为看门狗定时器建立超时周期。 每当按适当的顺序接收每个键值时，每次接收到指定的键值时，重新开始超时周期。 如果以不正确的顺序接收到一组键值，则会指示错误。 如果超时期间没有收到正确的键值序列，则指示超时。

    Watch dog timer and counter with multiple timeout periods
    4.
    发明授权
    Watch dog timer and counter with multiple timeout periods 有权
    看门狗定时器和计数器有多个超时时间

    公开(公告)号：US08458533B2

    公开(公告)日：2013-06-04

    申请号：US12939085

    申请日：2010-11-03

    申请人： Kevin Patrick Lavery

    发明人： Kevin Patrick Lavery

    IPC分类号： G06F11/00

    CPC分类号： G06F11/0757 ,  G06F11/0721

    摘要： A time-out period is established for a watchdog timer. The time-out period is restarted each time a designated key value is received when each key value is received in a proper sequence. An error is indicated if set of key values is received in an incorrect sequence. A time-out is indicated if a correct sequence of key values is not received within the time-out period.

    摘要翻译： 为看门狗定时器建立超时周期。 每当按适当的顺序接收每个键值时，每次接收到指定的键值时，重新开始超时周期。 如果以不正确的顺序接收到一组键值，则会指示错误。 如果超时期间没有收到正确的键值序列，则指示超时。

    Modulation Evaluation System
    6.
    发明申请
    Modulation Evaluation System 审中-公开
    调制评估系统

    公开(公告)号：US20110096820A1

    公开(公告)日：2011-04-28

    申请号：US12913643

    申请日：2010-10-27

    申请人： Kevin Patrick Lavery ,  Hari Pendurty

    发明人： Kevin Patrick Lavery ,  Hari Pendurty

    IPC分类号： H04B17/00

    CPC分类号： G06F1/10 ,  H03K2005/00052

    摘要： A modulation evaluation system associated with frequency modulations periods of a phase-locked loop is described. The system includes a first accumulator for accumulating clock edges a window of the frequency modulation periods; a second accumulator coupled to the first accumulator and operative for accumulating clock edges during whole periods of the frequency modulation periods; a dynamic enable control coupled to a first input associated with the first accumulator and a second input associated with the second accumulator, wherein the dynamic enable control selectively transmits a first enable signal that controls when the first accumulator accumulates clock edges and a second enable signal controls when the second accumulator accumulates clock edges, and accumulating clock edges enable modulation evaluation during production.

    摘要翻译： 描述了与锁相环的频率调制周期相关联的调制评估系统。 该系统包括用于在频率调制周期的窗口累积时钟沿的第一累加器; 耦合到所述第一累加器的第二累加器，用于在所述频率调制周期的整个周期期间累积时钟沿; 耦合到与所述第一累加器相关联的第一输入和与所述第二累加器相关联的第二输入的动态使能控制，其中所述动态使能控制选择性地发送第一使能信号，所述第一使能信号控制所述第一累加器何时累加时钟沿，以及第二使能信号控制 当第二个累加器累加时钟边沿时，并且累积时钟边沿使得在生产期间能够进行调制评估。