公开(公告)号：US07420846B2

公开(公告)日：2008-09-02

申请号：US10552948

申请日：2004-04-08

申请人： Jian Chen ,  Khandker N. Quader

发明人： Jian Chen ,  Khandker N. Quader

IPC分类号： G11C16/06

CPC分类号： G11C7/04 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/20 ,  G11C16/26 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2211/5621

摘要： In a non-volatile memory, the read parameter used to distinguish the data states characterized by a negative threshold voltage from the data states characterized by a positive threshold voltage is compensated for the memory's operating conditions, rather than being hardwired to ground. In an exemplary embodiment, the read parameter for the data state with the lowest threshold value above ground is temperature compensated to reflect the shifts of the storage element populations on either side of the read parameter. According to another aspect, an erase process is presented that can take advantage the operating condition compensated sensing parameter. As the sensing parameter is no longer fixed at a value corresponding to 0 volts, instead shifting according to operating conditions, a sufficient margin is provided for the various erase verify levels even at lowered operating voltages.

摘要翻译： 在非易失性存储器中，用于区分由负阈值电压表征的数据状态的读取参数与由正阈值电压表征的数据状态进行补偿，而不是硬连线到地。 在示例性实施例中，对于具有高于地面的最低阈值的数据状态的读取参数被温度补偿以反映存储元件群在读取参数的任一侧上的偏移。 根据另一方面，提出了可以利用操作条件补偿的感测参数的擦除过程。 由于感测参数不再固定为对应于0伏的值，而是根据工作条件进行移位，即使在降低的工作电压下，也为各种擦除验证电平提供足够的余量。

公开(公告)号：US06839281B2

公开(公告)日：2005-01-04

申请号：US10414132

申请日：2003-04-14

申请人： Jian Chen ,  Khandker N. Quader

发明人： Jian Chen ,  Khandker N. Quader

IPC分类号： G11C11/56 ,  G11C16/26 ,  G11C16/34 ,  G11C16/06

CPC分类号： G11C7/04 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/20 ,  G11C16/26 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2211/5621

摘要： In a non-volatile memory, the read parameter used to distinguish the data states characterized by a negative threshold voltage from the data states characterized by a positive threshold voltage is compensated for the memory's operating conditions, rather than being hardwired to ground. In an exemplary embodiment, the read parameter for the data state with the lowest threshold value above ground is temperature compensated to reflect the shifts of the storage element populations on either side of the read parameter. According to another aspect, an erase process is presented that can take advantage the operating condition compensated sensing parameter. As the sensing parameter is no longer fixed at a value corresponding to 0 volts, instead shifling according to operating conditions, a sufficient margin is provided for the various erase verify levels even at lowered operating voltages.

摘要翻译： 在非易失性存储器中，用于区分由负阈值电压表征的数据状态的读取参数与由正阈值电压表征的数据状态进行补偿，而不是硬连线到地。 在示例性实施例中，对于具有高于地面的最低阈值的数据状态的读取参数被温度补偿以反映存储元件群在读取参数的任一侧上的偏移。 根据另一方面，提出了可以利用操作条件补偿的感测参数的擦除过程。 由于感测参数不再固定在对应于0伏的值，而是根据工作条件进行移位，即使在降低的工作电压下，也为各种擦除验证电平提供足够的余量。

公开(公告)号：US07061798B2

公开(公告)日：2006-06-13

申请号：US10966451

申请日：2004-10-15

申请人： Jian Chen ,  Tomoharu Tanaka ,  Yupin Fong ,  Khandker N. Quader

发明人： Jian Chen ,  Tomoharu Tanaka ,  Yupin Fong ,  Khandker N. Quader

IPC分类号： G11C16/34

CPC分类号： G11C11/5628 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3404 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459

摘要： A non-volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates. The memory is operated to minimize the effect of charge coupled between adjacent floating gates, by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states. This increases the separation between states and/or allows more states to be included within a given storage window. An implementation that is described is for a NAND type of flash EEPROM.

公开(公告)号：US07046548B2

公开(公告)日：2006-05-16

申请号：US11055776

申请日：2005-02-09

申请人： Raul-Adrian Cernea ,  Khandker N. Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

发明人： Raul-Adrian Cernea ,  Khandker N. Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

IPC分类号： G11C16/04

CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418

摘要： Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.

摘要翻译： 考虑到电池之间的电容耦合，减少存储在多行存储器单元中的表观电荷水平的错误读数的技术。 第一行的所有页面都用第一遍编程，然后用第一遍编程第二相邻行的所有页面，之后第一行以第二遍编程，然后第三行的所有页面都被编程 第一遍，然后通过第二遍返回到第二行的程序，依次类推，跨越数组的行。 这最大程度地减少了通过稍后将数据写入存储器单元的相邻行中可能发生的对存储器单元行存储的视在电荷的影响。

公开(公告)号：US06870768B2

公开(公告)日：2005-03-22

申请号：US10923320

申请日：2004-08-20

申请人： Raul-Adrian Cernea ,  Khandker N. Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

发明人： Raul-Adrian Cernea ,  Khandker N. Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G11C16/04

CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418

摘要： Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.

摘要翻译： 考虑到电池之间的电容耦合，减少存储在多行存储器单元中的表观电荷水平的错误读数的技术。 第一行的所有页面都用第一遍编程，然后用第一遍编程第二相邻行的所有页面，之后第一行以第二遍编程，然后第三行的所有页面都被编程 第一遍，然后通过第二遍返回到第二行的程序，依次类推，跨越数组的行。 这最大程度地减少了通过稍后将数据写入存储器单元的相邻行中可能发生的对存储器单元行存储的视在电荷的影响。

公开(公告)号：US06807095B2

公开(公告)日：2004-10-19

申请号：US10323534

申请日：2002-12-18

申请人： Jian Chen ,  Tomoharu Tanaka ,  Yupin Fong ,  Khandker N. Quader

发明人： Jian Chen ,  Tomoharu Tanaka ,  Yupin Fong ,  Khandker N. Quader

IPC分类号： G11C1634

CPC分类号： G11C11/5628 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3404 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459

摘要： A non-volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates. The memory is operated to minimize the effect of charge coupled between adjacent floating gates, by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states. This increases the separation between states and/or allows more states to be included within a given storage window. An implementation that is described is for a NAND type of flash EEPROM.

摘要翻译： 具有每个具有至少一个存储元件的存储器单元阵列的非易失性存储器系统每个存储元件具有多个存储级别范围。 闪存电可擦除和可编程只读存储器（EEPROM）是示例，其中存储元件是电浮动栅极。 操作存储器以通过在相邻单元被编程之后第二次编程一些单元来最小化耦合在相邻浮动栅极之间的电荷的影响。 第二编程步骤还压缩至少一些编程状态下的电荷水平分布。 这增加了状态之间的分离和/或允许在给定的存储窗口内包含更多的状态。 所描述的实现方案是用于NAND型闪存EEPROM。

公开(公告)号：US06781877B2

公开(公告)日：2004-08-24

申请号：US10237426

申请日：2002-09-06

申请人： Raul-Adrian Cernea ,  Khandker N. Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

发明人： Raul-Adrian Cernea ,  Khandker N. Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

IPC分类号： G11C1604

CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418

摘要： Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.

摘要翻译： 考虑到电池之间的电容耦合，减少存储在多行存储器单元中的表观电荷水平的错误读数的技术。 第一行的所有页面都用第一遍编程，然后用第一遍编程第二相邻行的所有页面，之后第一行以第二遍编程，然后第三行的所有页面都被编程 第一遍，然后通过第二遍返回到第二行的程序，依次类推，跨越数组的行。 这最大程度地减少了通过稍后将数据写入存储器单元的相邻行中可能发生的对存储器单元行存储的视在电荷的影响。

公开(公告)号：US06522580B2

公开(公告)日：2003-02-18

申请号：US09893277

申请日：2001-06-27

申请人： Jian Chen ,  Tomoharu Tanaka ,  Yupin Fong ,  Khandker N. Quader

发明人： Jian Chen ,  Tomoharu Tanaka ,  Yupin Fong ,  Khandker N. Quader

IPC分类号： G11C1634

CPC分类号： G11C11/5628 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3404 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459

摘要： A non-volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates. The memory is operated to minimize the effect of charge coupled between adjacent floating gates, by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states. This increases the separation between states and/or allows more states to be included within a given storage window. An implementation that is described is for a NAND type of flash EEPROM.

公开(公告)号：US07224613B2

公开(公告)日：2007-05-29

申请号：US11205595

申请日：2005-08-16

申请人： Jian Chen ,  Tomoharu Tanaka ,  Yupin Fong ,  Khandker N. Quader

发明人： Jian Chen ,  Tomoharu Tanaka ,  Yupin Fong ,  Khandker N. Quader

IPC分类号： G11C16/34

CPC分类号： G11C11/5628 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3404 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459

摘要： A non-volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates. The memory is operated to minimize the effect of charge coupled between adjacent floating gates, by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states. This increases the separation between states and/or allows more states to be included within a given storage window. An implementation that is described is for a NAND type of flash EEPROM.

摘要翻译： 具有每个具有至少一个存储元件的存储器单元阵列的非易失性存储器系统每个存储元件具有多个存储级别范围。 闪存电可擦除和可编程只读存储器（EEPROM）是示例，其中存储元件是电浮动栅极。 操作存储器以通过在相邻单元被编程之后第二次编程一些单元来最小化耦合在相邻浮动栅极之间的电荷的影响。 第二编程步骤还压缩至少一些编程状态下的电荷水平分布。 这增加了状态之间的分离和/或允许在给定的存储窗口内包含更多的状态。 所描述的实现方案是用于NAND型闪存EEPROM。

公开(公告)号：US06696880B2

公开(公告)日：2004-02-24

申请号：US10014161

申请日：2001-11-09

申请人： Feng Pan ,  Khandker N. Quader

发明人： Feng Pan ,  Khandker N. Quader

IPC分类号： H03K1716

CPC分类号： G11C5/145 ,  H03K17/063

摘要： The invention utilizes a boost-strap method to improve switch operation in a design that is particularly advantageous for supplying high voltages within a low voltage design. A native NMOS transistor, a PMOS transistor, and a capacitor are connected in series between the high voltage source and the output, where the gate of the native NMOS is connect to the output. In an initialization phase, the plate of the capacitor connected to the output is precharged by receiving the input signal while the other plate of the capacitor is held near ground. In a subsequent enable phase, the native NMOS and PMOS transistors are turned on and the high voltage is supplied to the output.

摘要翻译： 本发明利用升压带方法来改进对于在低电压设计中提供高电压特别有利的设计中的开关操作。 天线NMOS晶体管，PMOS晶体管和电容器串联连接在高电压源和输出端之间，其中天线NMOS的栅极连接到输出端。 在初始化阶段，连接到输出端的电容器的板通过接收输入信号而被预充电，而电容器的另一个板保持靠近地。 在随后的使能阶段，天线NMOS和PMOS晶体管导通，高压被提供给输出。