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    Phase-change memory device
    1.
    发明授权
    Phase-change memory device 有权
    相变存储器件

    公开(公告)号：US08248844B2

    公开(公告)日：2012-08-21

    申请号：US13347021

    申请日：2012-01-10

    Applicant: Ki-won Lim ,  Won-ryul Chung ,  Young-ran Kim

    Inventor： Ki-won Lim ,  Won-ryul Chung ,  Young-ran Kim

    IPC: G11C11/00

    CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/0083 ,  Y10S977/754

    Abstract: A phase-change memory device and its firing method are provided. The firing method of the phase-change memory device includes applying a writing current to phase-change memory cells, identifying a state of the phase-change memory cells after applying the writing current, and applying a firing current, in which an additional current is added to the writing current, to the phase-change memory cells in accordance with the state.

    Abstract translation: 提供了相变存储器件及其烧制方法。 相变存储装置的点火方法包括向相变存储单元施加写入电流，在施加写入电流之后识别相变存储单元的状态，并施加额外电流为 根据该状态将相加变换存储单元加到写入电流上。

    Semiconductor memory device having an interconnect structure which improves yield
    3.
    发明授权
    Semiconductor memory device having an interconnect structure which improves yield 失效
    具有提高产量的互连结构的半导体存储器件

    公开(公告)号：US5763908A

    公开(公告)日：1998-06-09

    申请号：US687925

    申请日：1996-07-29

    Applicant: Eui-Gyn Han ,  Kwang-suk Ryu ,  Ki-won Lim

    Inventor： Eui-Gyn Han ,  Kwang-suk Ryu ,  Ki-won Lim

    IPC: H01L27/06 ,  G11C11/40 ,  G11C11/401 ,  G11C11/407 ,  H01L21/3205 ,  H01L21/8234 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/10 ,  H01L27/108 ,  H01L27/11

    CPC classification number: H01L27/10805 ,  H01L27/11

    Abstract: A semiconductor memory device in which word lines are arranged so as to improve the yield with respect to bridging defects. The semiconductor memory device of the present invention has a plurality of interconnects arranged in parallel on a cell array portion, in which the interconnects are comprised of power lines and ground lines arranged alternately on the cell array portion, main word lines arranged on each side of the power lines, and a plurality of block word lines sequentially arranged between a single main word line and a ground line adjacent thereto and controlled by the main word line. In this way, interconnects are arranged in alternating groups so that interconnects having the same logic level during the standby mode are grouped together. The result of this arrangement is that interconnect bridges within a group will not lead to increased standby current, thereby substantially improving the yield of the semiconductor memory device. In addition, the spacing between groups of interconnects may be increased, further reducing the probability of increased standby current due to a bridging defect, thereby further increasing the yield.

    Abstract translation: 一种半导体存储器件，其中布置字线以提高相对于桥接缺陷的产量。 本发明的半导体存储装置具有在单元阵列部分上并联布置的多个互连，其中互连由交替设置在单元阵列部分上的电源线和接地线组成，主字线布置在 电源线和顺序地布置在单个主字线和与其相邻并由主字线控制的地线之间的多个块字线。 以这种方式，互连以交替的组布置，使得在待机模式期间具有相同逻辑电平的互连被分组在一起。 这种布置的结果是组内的互连桥不会导致待机电流的增加，从而显着提高了半导体存储器件的产量。 此外，可以增加互连组之间的间隔，进一步降低由于桥接缺陷引起的备用电流增加的可能性，从而进一步提高产量。

    Nonvolatile memory devices having variable-resistance memory cells and methods of programming the same
    4.
    发明授权
    Nonvolatile memory devices having variable-resistance memory cells and methods of programming the same 有权
    具有可变电阻存储单元的非易失性存储器件及其编程方法

    公开(公告)号：US08199603B2

    公开(公告)日：2012-06-12

    申请号：US12498549

    申请日：2009-07-07

    Applicant: Won-Ryul Chung ,  Byung-Gil Choi ,  In-Cheol Shin ,  Ki-Won Lim

    Inventor： Won-Ryul Chung ,  Byung-Gil Choi ,  In-Cheol Shin ,  Ki-Won Lim

    IPC: G11C8/00

    CPC classification number: G11C13/0038 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/72 ,  G11C2213/79

    Abstract: Nonvolatile memory devices include an array of variable-resistance memory cells and a write driver electrically coupled to the array. The write driver is configured to drive a bit line in the array of variable-resistance memory cells with a stair-step sequence of at least two unequal bit line voltages during an operation to program a variable-resistance memory cell in said array. This stair-step sequence of at least two unequal bit line voltages includes a precharge voltage (e.g., Vcc-Vth) at a first step and a higher boosted voltage (e.g., Vpp-Vth) at a second step that follows the first step.

    Abstract translation: 非易失性存储器件包括可变电阻存储器单元阵列和电耦合到阵列的写入驱动器。 写入驱动器被配置为在用于编程所述阵列中的可变电阻存储器单元的操作期间，在具有至少两个不相等的位线电压的阶梯序列的驱动可变电阻存储器单元阵列中的位线。 至少两个不等位线电压的阶梯级序列包括第一步骤的预充电电压（例如Vcc-Vth）和跟随第一步骤的第二步骤的较高升压电压（例如，Vpp-Vth）。

    Phase-change memory device and firing method for the same
    6.
    发明授权
    Phase-change memory device and firing method for the same 有权
    相变存储器件和烧制方法相同

    公开(公告)号：US08111545B2

    公开(公告)日：2012-02-07

    申请号：US11902727

    申请日：2007-09-25

    Applicant: Ki-won Lim ,  Won-ryul Chung ,  Young-ran Kim

    Inventor： Ki-won Lim ,  Won-ryul Chung ,  Young-ran Kim

    IPC: G11C11/00

    CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/0083 ,  Y10S977/754

    Abstract: A phase-change memory device and its firing method are provided. The firing method of the phase-change memory device includes applying a writing current to phase-change memory cells, identifying a state of the phase-change memory cells after applying the writing current, and applying a firing current, in which an additional current is added to the writing current, to the phase-change memory cells in accordance with the state.

    Abstract translation: 提供了相变存储器件及其烧制方法。 相变存储装置的点火方法包括向相变存储单元施加写入电流，在施加写入电流之后识别相变存储单元的状态，并施加额外电流为 根据该状态将相加变换存储单元加到写入电流上。

    Phase-change memory device and firing method for the same
    8.
    发明申请
    Phase-change memory device and firing method for the same 有权
    相变存储器件和烧制方法相同

    公开(公告)号：US20080074919A1

    公开(公告)日：2008-03-27

    申请号：US11902727

    申请日：2007-09-25

    Applicant: Ki-won Lim ,  Won-ryul Chung ,  Young-ran Kim

    Inventor： Ki-won Lim ,  Won-ryul Chung ,  Young-ran Kim

    IPC: G11C11/4091

    CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/0083 ,  Y10S977/754

    Abstract: A phase-change memory device and its firing method are provided. The firing method of the phase-change memory device includes applying a writing current to phase-change memory cells, identifying a state of the phase-change memory cells after applying the writing current, and applying a firing current, in which an additional current is added to the writing current, to the phase-change memory cells in accordance with the state.

    Abstract translation: 提供了相变存储器件及其烧制方法。 相变存储装置的点火方法包括向相变存储单元施加写入电流，在施加写入电流之后识别相变存储单元的状态，并施加额外电流为 根据该状态将相加变换存储单元加到写入电流上。

    PHASE-CHANGE MEMORY DEVICE
    9.
    发明申请
    PHASE-CHANGE MEMORY DEVICE 有权
    相变存储器件

    公开(公告)号：US20120106244A1

    公开(公告)日：2012-05-03

    申请号：US13347021

    申请日：2012-01-10

    Applicant: Ki-won Lim ,  Won-ryul Chung ,  Young-ran Kim

    Inventor： Ki-won Lim ,  Won-ryul Chung ,  Young-ran Kim

    IPC: G11C11/00

    CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/0083 ,  Y10S977/754

    Abstract: A phase-change memory device and its firing method are provided. The firing method of the phase-change memory device includes applying a writing current to phase-change memory cells, identifying a state of the phase-change memory cells after applying the writing current, and applying a firing current, in which an additional current is added to the writing current, to the phase-change memory cells in accordance with the state.

    Abstract translation: 提供了相变存储器件及其烧制方法。 相变存储装置的点火方法包括向相变存储单元施加写入电流，在施加写入电流之后识别相变存储单元的状态，并施加额外电流为 根据该状态将相加变换存储单元加到写入电流上。

    Integrated circuit devices using fuse elements to generate an output signal that is independent of cut fuse remnants
    10.
    发明授权
    Integrated circuit devices using fuse elements to generate an output signal that is independent of cut fuse remnants 失效
    使用熔丝元件产生独立于切断的熔丝残留物的输出信号的集成电路器件

    公开(公告)号：US06201432B1

    公开(公告)日：2001-03-13

    申请号：US09315695

    申请日：1999-05-20

    Applicant: Ki-Won Lim ,  Eui-Gyu Han ,  Jeong-Un Choi

    Inventor： Ki-Won Lim ,  Eui-Gyu Han ,  Jeong-Un Choi

    IPC: H01H3776

    CPC classification number: G11C17/18

    Abstract: Integrated circuit devices include a comparator circuit and a fuse programmable input circuit. The fuse programmable input circuit generates first and second differential input signals at voltage levels that can be controlled through a pair of fuses. The comparator circuit generates an output signal based on the relative voltage levels exhibited by the first and second differential input signals. In particular, the output signal is driven to a first logic state when the voltage difference between the first and second differential input signals is positive and the output signal is driven to a second logic state, which is opposite the first logic state, when the voltage difference is negative. Because the comparator is responsive to the relative difference between the voltage levels of the first and second differential input signals and not the absolute magnitudes of the voltage levels, fuse remnants that may exist after the fuse programmable input circuit has been programmed (i.e., one or more fuses have been cut) typically do not affect the output signal.

    Abstract translation: 集成电路器件包括比较器电路和熔丝可编程输入电路。 保险丝可编程输入电路在可通过一对保险丝控制的电压电平下产生第一和第二差分输入信号。 比较器电路基于由第一和第二差分输入信号表现的相对电压电平产生输出信号。 具体地，当第一和第二差分输入信号之间的电压差为正时，输出信号被驱动到第一逻辑状态，并且当电压与第一逻辑状态相反时，输出信号被驱动到第二逻辑状态 差异为负数。 因为比较器响应于第一和第二差分输入信号的电压电平之间的相对差异而不是电压电平的绝对值，所以在熔丝可编程输入电路已被编程之后可能存在的熔丝残余物（即，一个或多个 更多的保险丝被切断）通常不影响输出信号。

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