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    Semiconductor integrated circuit device having a compact arrangement of SRAM cells
    3.
    发明授权
    Semiconductor integrated circuit device having a compact arrangement of SRAM cells 失效
    具有紧凑的SRAM单元布置的半导体集成电路器件

    公开(公告)号：US5396100A

    公开(公告)日：1995-03-07

    申请号：US861366

    申请日：1992-03-31

    申请人： Kohji Yamasaki ,  Nobuyuki Moriwaki ,  Shuji Ikeda ,  Hideaki Nakamura ,  Shigeru Honjo

    发明人： Kohji Yamasaki ,  Nobuyuki Moriwaki ,  Shuji Ikeda ,  Hideaki Nakamura ,  Shigeru Honjo

    IPC分类号： H01L27/02 ,  H01L27/11 ,  H01L29/76 ,  H01L23/552 ,  H01L27/10

    CPC分类号： H01L27/1108 ,  H01L27/0207 ,  H01L27/1104 ,  H01L2924/0002 ,  Y10S257/903

    摘要： Herein disclosed is a semiconductor integrated circuit device which has a memory array or a memory mat formed of memory cells arranged regularly in a matrix shape. At the end portion or inside of the memory array or memory cell in the region of the device where the patterning of the memory cells is discontinued or interrupted, the shape of an element isolating insulating film, which is formed for regulating the memory cells having pattern interruptions, is made substantially identical to the shape of the element isolating insulating film for regulating the memory cells in the region of the device where the patternings of the memory cells are of an uninterrupted regular form. In the location on the chip front face where the regular patterns associated with the memory area are discontinued, there is formed a dummy pattern having a shape made substantially identical to that of a gate electrode arranged at the end portion of the location where the regular patterns are interrupted.

    摘要翻译： 这里公开了一种半导体集成电路器件，其具有由矩阵形状规则地排列的存储单元形成的存储器阵列或存储器垫。 在存储器单元的图案化中断或中断的器件的区域中的存储器阵列或存储单元的端部或内部，形成用于调节具有图案的存储单元的元件隔离绝缘膜的形状 使得与存储单元的图形不间断规则形式的装置区域中用于调节存储单元的元件隔离绝缘膜的形状基本相同。 在与存储区域相关联的规则图案的芯片正面上的位置中断的情况下，形成具有与布置在位置的端部的栅电极的形状基本相同的形状的虚设图案，其中规则图案 被中断。