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    Semiconductor integrated circuit device
    2.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US06586807B2

    公开(公告)日：2003-07-01

    申请号：US09774717

    申请日：2001-02-01

    申请人： Akio Nishida ,  Noriyuki Yabuoshi ,  Yasuko Yoshida ,  Kazuhiro Komori ,  Sousuke Tsuji ,  Hideo Miwa ,  Mitsuhiro Higuchi ,  Koichi Imato

    发明人： Akio Nishida ,  Noriyuki Yabuoshi ,  Yasuko Yoshida ,  Kazuhiro Komori ,  Sousuke Tsuji ,  Hideo Miwa ,  Mitsuhiro Higuchi ,  Koichi Imato

    IPC分类号： H01L2976

    CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L27/105 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4238

    摘要： A gate electrode of each MISFET is formed on a substrate in an active region whose periphery is defined by an element isolation trench, and crosses the active region so as to extend from one end thereof to the other end thereof. The gate electrode has a gate length in a boundary region defined between the active region and the element isolation trench which is greater than a gate length in a central portion of the active region. The gate electrode is configured in an H-type flat pattern. Further, the gate electrode covers the whole of one side extending along a gate-length direction, of the boundary region defined between the active region L and the element isolation trench, and parts of two sides thereof extending along a gate-width direction. The MISFETs are formed in electrically separated wells and are connected in series to constitute part of a reference voltage generating circuit.

    摘要翻译： 每个MISFET的栅电极形成在其周围由元件隔离沟槽限定的有源区中的衬底上，并且穿过有源区从其一端延伸到另一端。 栅极电极在有源区域和元件隔离沟槽之间限定的边界区域中的栅极长度大于有源区域的中心部分中的栅极长度。 栅电极配置为H型平面图案。 此外，栅电极覆盖沿着栅极长度方向延伸的整个一侧，限定在有源区域L和元件隔离沟槽之间的边界区域以及沿栅极宽度方向延伸的两侧的部分。 MISFET形成在电分离的阱中并且串联连接以构成参考电压产生电路的一部分。