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    High speed semiconductor memory device having a high gain sense amplifier
    3.
    再颁专利
    High speed semiconductor memory device having a high gain sense amplifier 失效

    公开(公告)号：USRE34060E

    公开(公告)日：1992-09-08

    申请号：US359684

    申请日：1989-05-31

    申请人： Nobuyoshi Tanimura ,  Sho Yamamoto ,  Kazuo Yoshizaki ,  Isao Akima

    发明人： Nobuyoshi Tanimura ,  Sho Yamamoto ,  Kazuo Yoshizaki ,  Isao Akima

    IPC分类号： G11C11/419 ,  H03F3/45 ,  H03F3/72 ,  H03K5/02 ,  H03K5/24

    CPC分类号： G11C11/419 ,  H03F3/45475 ,  H03F3/72 ,  H03K5/023 ,  H03K5/2481

    摘要： In a static type RAM, a sense amplifier includes first and second dissymmetric type differential amplifier circuits each of which has a pair of differential transistors and an active load circuit such as a current mirror circuit connected to the drains of the differential transistors. One of balanced signals delivered from a memory cell is supplied to the non-inverting input terminal of the first dissymmetric type differential amplifier circuit and the inverting input terminal of the second dissymmetric type differential amplifier circuit. The other of said balanced signals is applied to the remaining input terminals of the first and second dissymmetric type differential amplifier circuits. As a result, notwithstanding that balanced signals cannot be delivered from each dissymmetric type differential amplifier circuit, amplified balanced signals can be obtained. The operating speed of the RAM can be raised owing to the fact that the dissymmetric type differential amplifier circuit having an active load circuit exhibits a comparatively high gain and the fact that the signal amplification by the balanced circuit is permitted.

    High speed semiconductor memory device having a high gain sense amplifier
    8.
    发明授权
    High speed semiconductor memory device having a high gain sense amplifier 失效
    具有高增益读出放大器的高速半导体存储器件

    公开(公告)号：US4509147A

    公开(公告)日：1985-04-02

    申请号：US383945

    申请日：1982-06-01

    申请人： Nobuyoshi Tanimura ,  Sho Yamamoto ,  Kazuo Yoshizaki ,  Isao Akima

    发明人： Nobuyoshi Tanimura ,  Sho Yamamoto ,  Kazuo Yoshizaki ,  Isao Akima

    IPC分类号： G11C7/06 ,  G11C11/419 ,  H03F3/45 ,  H03F3/72 ,  G11C11/34

    CPC分类号： H03F3/72 ,  G11C11/419 ,  G11C7/06 ,  H03F3/45475

    摘要： In a static type RAM, a sense amplifier includes first and second dissymmetric type differential amplifier circuits each of which has a pair of differential transistors and an active load circuit such as a current mirror circuit connected to the drains of the differential transistors. One of balanced signals delivered from a memory cell is supplied to the non-inverting input terminal of the first dissymmetric type differential amplifier circuit and the inverting input terminal of the second dissymmetric type differential amplifier circuit. The other of said balanced signals is applied to the remaining input terminals of the first and second dissymmetric type differential amplifier circuits. As a result, notwithstanding that balanced signals cannot be delivered from each dissymmetric type differential amplifier circuit, amplified balanced signals can be obtained. The operating speed of the RAM can be raised owing to the fact that the dissymmetric type differential amplifier circuit having an active load circuit exhibits a comparatively high gain and the fact that the signal amplification by the balanced circuit is permitted.

    摘要翻译： 在静态RAM中，读出放大器包括第一和第二非对称型差分放大器电路，每个差分放大器具有一对差分晶体管和有源负载电路，例如连接到差分晶体管的漏极的电流镜电路。 从存储单元发送的平衡信号中的一个被提供给第一非对称型差分放大器电路的非反相输入端子和第二非对称型差分放大器电路的反相输入端子。 所述平衡信号中的另一个被施加到第一和第二非对称型差分放大器电路的剩余输入端。 结果，尽管不能从每个非对称型差分放大器电路输出平衡信号，但是可以获得放大的平衡信号。 由于具有有源负载电路的非对称型差分放大器电路具有相对较高的增益以及允许由平衡电路进行信号放大的事实，所以可以提高RAM的工作速度。