公开(公告)号：US5880497A

公开(公告)日：1999-03-09

申请号：US592235

申请日：1996-01-26

申请人： Shuji Ikeda ,  Koichi Imato ,  Kazuo Yoshizaki ,  Kohji Yamasaki ,  Soichiro Hashiba ,  Keiichi Yoshizumi ,  Yasuko Yoshida ,  Kousuke Okuyama ,  Mitsugu Oshima ,  Kazushi Tomita ,  Tsuyoshi Tabata ,  Kazushi Fukuda ,  Junichi Takano ,  Toshiaki Yamanaka ,  Chiemi Hashimoto ,  Motoko Kawashima ,  Fumiyuki Kanai ,  Takashi Hashimoto

发明人： Shuji Ikeda ,  Koichi Imato ,  Kazuo Yoshizaki ,  Kohji Yamasaki ,  Soichiro Hashiba ,  Keiichi Yoshizumi ,  Yasuko Yoshida ,  Kousuke Okuyama ,  Mitsugu Oshima ,  Kazushi Tomita ,  Tsuyoshi Tabata ,  Kazushi Fukuda ,  Junichi Takano ,  Toshiaki Yamanaka ,  Chiemi Hashimoto ,  Motoko Kawashima ,  Fumiyuki Kanai ,  Takashi Hashimoto

IPC分类号： H01L27/11

CPC分类号： H01L27/1108 ,  Y10S257/903 ,  Y10S257/904

摘要： A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.

摘要翻译： 其存储单元被构造成包括由字线控制的转移MISFET和具有驱动器MISFET和负载MISFET的触发器电路的SRAM。 固定在预定电源线上的大面积平板电极布置在负载MISFET上，使得负载MISFET的偏移区域上的平板电极形成开口。 在半导体衬底的主表面上形成的转移MISFET和驱动器MISFET上形成具有可渗透氢而不湿度的氮化硅膜，以及沉积在驱动器MISFET上的多晶硅膜形成的负载MISFET。

公开(公告)号：US5508540A

公开(公告)日：1996-04-16

申请号：US190596

申请日：1994-02-02

申请人： Shuji Ikeda ,  Koichi Imato ,  Kazuo Yoshizaki ,  Kohji Yamasaki ,  Soichiro Hashiba ,  Keiichi Yoshizumi ,  Yasuko Yoshida ,  Kousuke Okuyama ,  Mitsugu Oshima ,  Kazushi Tomita ,  Tsuyoshi Tabata ,  Kazushi Fukuda ,  Junichi Takano ,  Toshiaki Yamanaka ,  Chiemi Hashimoto ,  Motoko Kawashima ,  Fumiyuki Kanai ,  Takashi Hashimoto

发明人： Shuji Ikeda ,  Koichi Imato ,  Kazuo Yoshizaki ,  Kohji Yamasaki ,  Soichiro Hashiba ,  Keiichi Yoshizumi ,  Yasuko Yoshida ,  Kousuke Okuyama ,  Mitsugu Oshima ,  Kazushi Tomita ,  Tsuyoshi Tabata ,  Kazushi Fukuda ,  Junichi Takano ,  Toshiaki Yamanaka ,  Chiemi Hashimoto ,  Motoko Kawashima ,  Fumiyuki Kanai ,  Takashi Hashimoto

IPC分类号： H01L27/11 ,  H01L27/108 ,  H01L29/04 ,  H01L29/76

CPC分类号： H01L27/1108 ,  Y10S257/903 ,  Y10S257/904

摘要： A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.

摘要翻译： 其存储单元被构造成包括由字线控制的转移MISFET和具有驱动器MISFET和负载MISFET的触发器电路的SRAM。 固定在预定电源线上的大面积平板电极布置在负载MISFET上，使得负载MISFET的偏移区域上的平板电极形成开口。 在半导体衬底的主表面上形成的转移MISFET和驱动器MISFET上形成具有可渗透氢而不湿度的氮化硅膜，以及沉积在驱动器MISFET上的多晶硅膜形成的负载MISFET。

公开(公告)号：US06777279B2

公开(公告)日：2004-08-17

申请号：US10412230

申请日：2003-04-14

申请人： Chiemi Hashimoto ,  Yasuhiko Kawashima ,  Keizo Kawakita ,  Masahiro Moniwa ,  Hiroyasu Ishizuka ,  Akihiro Shimizu

发明人： Chiemi Hashimoto ,  Yasuhiko Kawashima ,  Keizo Kawakita ,  Masahiro Moniwa ,  Hiroyasu Ishizuka ,  Akihiro Shimizu

IPC分类号： H01L21336

CPC分类号： H01L27/10894 ,  H01L21/823857 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10873 ,  H01L28/91

摘要： Disclosed are a semiconductor integrated circuit device and a method of manufacturing the same capable of realizing the two-level gate insulator process for the DRAM without increasing the number of manufacturing steps and that of photomasks. After forming a gate electrode of a MISFET which constitutes a memory cell in a memory array region on a semiconductor substrate, the substrate is subjected to thermal treatment (re-oxidation process). At this time, since bird's beak of the thick gate insulating film formed below the sidewall portion of the gate electrode penetrates into the center of the gate electrode, a gate insulating film thicker than the gate insulating film before the re-oxidation process is formed just below the center of the gate electrode. Meanwhile, since the gate electrode in the peripheral circuit region has a gate length longer than that of the gate electrode in the memory array region, the thickness of the gate insulating film just below the center thereof is almost equal to that before the re-oxidation process.

公开(公告)号：US08106478B2

公开(公告)日：2012-01-31

申请号：US12014132

申请日：2008-01-15

申请人： Chiemi Hashimoto ,  Toshio Yamada

发明人： Chiemi Hashimoto ,  Toshio Yamada

IPC分类号： H01L29/94

CPC分类号： H01L27/0629 ,  H01L27/0207 ,  H01L27/11898 ,  H01L2924/0002 ,  H01L2924/00

摘要： A power source noise of a semiconductor device having a core cell configuring a logic circuit is reduced. Above the core cell configuring the logic circuit provided on a main surface of a semiconductor substrate are provided a first branch line for a first power source of the core cell, which is electrically connected to a first power source trunk line, and a second branch line for a second power source of the core cell, which is electrically connected to a second power source trunk line. The first and second branch lines are oppositely provided, thereby forming a capacitor between the first and second power sources.

摘要翻译： 具有构成逻辑电路的核心单元的半导体器件的电源噪声减小。 配置设置在半导体基板的主表面上的逻辑电路的核心单元上方设置有用于核心单元的第一电源的第一分支线，其与第一电源主干线电连接，第二分支线 用于核心单元的第二电源，其电连接到第二电源干线。 第一和第二支线相对地设置，从而在第一和第二电源之间形成电容器。